upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
1.3 KiB
61 lines
1.3 KiB
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm APQ8096
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*
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* (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
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*
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* Based on Little Kernel driver, simplified
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(30)
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#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
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static const struct bcr_regs sdc_regs = {
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.cfg_rcgr = SDCC2_CFG_RCGR,
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.cmd_rcgr = SDCC2_CMD_RCGR,
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.M = SDCC2_M,
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.N = SDCC2_N,
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.D = SDCC2_D,
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};
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static const struct pll_vote_clk gpll0_vote_clk = {
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.status = GPLL0_STATUS,
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.status_bit = GPLL0_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
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};
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static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
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{
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int div = 3;
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clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
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clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
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CFG_CLK_SRC_GPLL0);
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
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return rate;
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}
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ulong msm_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0: /* SDC1 */
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return clk_init_sdc(priv, rate);
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break;
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default:
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return 0;
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}
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}
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