upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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59 lines
1.5 KiB
59 lines
1.5 KiB
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <common.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/io.h>
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#include <asm/arch/handoff_s10.h>
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#include <asm/arch/system_manager.h>
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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const struct cm_config * const cm_get_default_config(void)
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{
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struct cm_config *cm_handoff_cfg = (struct cm_config *)
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(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
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u32 *conversion = (u32 *)cm_handoff_cfg;
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u32 i;
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u32 handoff_clk = readl(S10_HANDOFF_CLOCK);
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if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) {
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writel(swab32(handoff_clk), S10_HANDOFF_CLOCK);
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for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
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conversion[i] = swab32(conversion[i]);
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return cm_handoff_cfg;
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} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
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return cm_handoff_cfg;
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}
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return NULL;
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}
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const unsigned int cm_get_osc_clk_hz(void)
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{
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#ifdef CONFIG_SPL_BUILD
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u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
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writel(clock, &sysmgr_regs->boot_scratch_cold1);
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#endif
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return readl(&sysmgr_regs->boot_scratch_cold1);
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}
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const unsigned int cm_get_intosc_clk_hz(void)
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{
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return CLKMGR_INTOSC_HZ;
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}
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const unsigned int cm_get_fpga_clk_hz(void)
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{
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#ifdef CONFIG_SPL_BUILD
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u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
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writel(clock, &sysmgr_regs->boot_scratch_cold2);
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#endif
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return readl(&sysmgr_regs->boot_scratch_cold2);
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}
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