upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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414 lines
11 KiB
414 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/scu.h>
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#include "cpu.h"
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int get_num_cpus(void)
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{
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struct apb_misc_gp_ctlr *gp;
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uint rev;
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debug("%s entry\n", __func__);
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gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
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switch (rev) {
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case CHIPID_TEGRA20:
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return 2;
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break;
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case CHIPID_TEGRA30:
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case CHIPID_TEGRA114:
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case CHIPID_TEGRA124:
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case CHIPID_TEGRA210:
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default:
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return 4;
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break;
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}
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}
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/*
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* Timing tables for each SOC for all four oscillator options.
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*/
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struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
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/*
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* T20: 1 GHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 22:20 3
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* PLLX_BASE n 17: 8 10
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* PLLX_BASE m 4: 0 5
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* PLLX_MISC cpcon 11: 8 4
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*/
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{
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{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
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{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
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{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
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{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
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{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
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{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
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},
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/*
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* T25: 1.2 GHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 22:20 3
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* PLLX_BASE n 17: 8 10
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* PLLX_BASE m 4: 0 5
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* PLLX_MISC cpcon 11: 8 4
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*/
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{
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{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
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{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
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{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
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{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
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{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
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{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
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},
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/*
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* T30: 600 MHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 22:20 3
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* PLLX_BASE n 17: 8 10
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* PLLX_BASE m 4: 0 5
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* PLLX_MISC cpcon 11: 8 4
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*/
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{
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{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
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{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
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{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
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{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
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{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
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{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
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},
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/*
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* T114: 700 MHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 23:20 4
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* PLLX_BASE n 15: 8 8
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* PLLX_BASE m 7: 0 8
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*/
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{
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{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
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{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
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{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
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{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
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{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
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{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
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},
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/*
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* T124: 700 MHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 23:20 4
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* PLLX_BASE n 15: 8 8
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* PLLX_BASE m 7: 0 8
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*/
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{
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{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
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{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
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{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
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{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
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{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
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{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
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},
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/*
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* T210: 700 MHz
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*
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* Register Field Bits Width
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* ------------------------------
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* PLLX_BASE p 24:20 5
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* PLLX_BASE n 15: 8 8
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* PLLX_BASE m 7: 0 8
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*/
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{
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{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
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{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
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{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
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{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
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{ .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
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{ .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
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},
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};
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static inline void pllx_set_iddq(void)
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{
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#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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debug("%s entry\n", __func__);
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/* Disable IDDQ */
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reg = readl(&clkrst->crc_pllx_misc3);
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reg &= ~PLLX_IDDQ_MASK;
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writel(reg, &clkrst->crc_pllx_misc3);
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udelay(2);
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debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
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readl(&clkrst->crc_pllx_misc3));
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#endif
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}
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int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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u32 divp, u32 cpcon)
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{
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struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
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int chip = tegra_get_chip();
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u32 reg;
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debug("%s entry\n", __func__);
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/* If PLLX is already enabled, just return */
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if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
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debug("%s: PLLX already enabled, returning\n", __func__);
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return 0;
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}
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pllx_set_iddq();
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/* Set BYPASS, m, n and p to PLLX_BASE */
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reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
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reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
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writel(reg, &pll->pll_base);
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/* Set cpcon to PLLX_MISC */
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if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
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reg = (cpcon << pllinfo->kcp_shift);
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else
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reg = 0;
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/*
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* TODO(twarren@nvidia.com) Check which SoCs use DCCON
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* and add to pllinfo table if needed!
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*/
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/* Set dccon to PLLX_MISC if freq > 600MHz */
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if (divn > 600)
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reg |= (1 << PLL_DCCON_SHIFT);
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writel(reg, &pll->pll_misc);
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/* Disable BYPASS */
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reg = readl(&pll->pll_base);
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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debug("%s: base = 0x%08X\n", __func__, reg);
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/* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
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reg = readl(&pll->pll_misc);
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if (pllinfo->lock_ena < 32)
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reg |= (1 << pllinfo->lock_ena);
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writel(reg, &pll->pll_misc);
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debug("%s: misc = 0x%08X\n", __func__, reg);
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/* Enable PLLX last, once it's all configured */
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reg = readl(&pll->pll_base);
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reg |= PLL_ENABLE_MASK;
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writel(reg, &pll->pll_base);
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debug("%s: base final = 0x%08X\n", __func__, reg);
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return 0;
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}
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void init_pllx(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
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int soc_type, sku_info, chip_sku;
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enum clock_osc_freq osc;
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struct clk_pll_table *sel;
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debug("%s entry\n", __func__);
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/* get SOC (chip) type */
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soc_type = tegra_get_chip();
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debug("%s: SoC = 0x%02X\n", __func__, soc_type);
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/* get SKU info */
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sku_info = tegra_get_sku_info();
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debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
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/* get chip SKU, combo of the above info */
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chip_sku = tegra_get_chip_sku();
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debug("%s: Chip SKU = %d\n", __func__, chip_sku);
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/* get osc freq */
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osc = clock_get_osc_freq();
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debug("%s: osc = %d\n", __func__, osc);
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/* set pllx */
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sel = &tegra_pll_x_table[chip_sku][osc];
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pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
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}
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void enable_cpu_clock(int enable)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 clk;
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debug("%s entry\n", __func__);
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/*
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* NOTE:
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* Regardless of whether the request is to enable or disable the CPU
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* clock, every processor in the CPU complex except the master (CPU 0)
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* will have it's clock stopped because the AVP only talks to the
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* master.
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*/
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if (enable) {
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/* Initialize PLLX */
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init_pllx();
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/* Wait until all clocks are stable */
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udelay(PLL_STABILIZATION_DELAY);
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
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}
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/*
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* Read the register containing the individual CPU clock enables and
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* always stop the clocks to CPUs > 0.
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*/
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clk = readl(&clkrst->crc_clk_cpu_cmplx);
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clk |= 1 << CPU1_CLK_STP_SHIFT;
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if (get_num_cpus() == 4)
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clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
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/* Stop/Unstop the CPU clock */
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clk &= ~CPU0_CLK_STP_MASK;
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clk |= !enable << CPU0_CLK_STP_SHIFT;
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writel(clk, &clkrst->crc_clk_cpu_cmplx);
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clock_enable(PERIPH_ID_CPU);
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}
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static int is_cpu_powered(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
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}
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static void remove_cpu_io_clamps(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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debug("%s entry\n", __func__);
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/* Remove the clamps on the CPU I/O signals */
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reg = readl(&pmc->pmc_remove_clamping);
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reg |= CPU_CLMP;
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writel(reg, &pmc->pmc_remove_clamping);
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/* Give I/O signals time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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}
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void powerup_cpu(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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int timeout = IO_STABILIZATION_DELAY;
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debug("%s entry\n", __func__);
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if (!is_cpu_powered()) {
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/* Toggle the CPU power state (OFF -> ON) */
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reg = readl(&pmc->pmc_pwrgate_toggle);
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reg &= PARTID_CP;
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reg |= START_CP;
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writel(reg, &pmc->pmc_pwrgate_toggle);
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/* Wait for the power to come up */
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while (!is_cpu_powered()) {
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if (timeout-- == 0)
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printf("CPU failed to power up!\n");
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else
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udelay(10);
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}
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/*
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* Remove the I/O clamps from CPU power partition.
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* Recommended only on a Warm boot, if the CPU partition gets
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* power gated. Shouldn't cause any harm when called after a
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* cold boot according to HW, probably just redundant.
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*/
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remove_cpu_io_clamps();
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}
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}
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void reset_A9_cpu(int reset)
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{
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset
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* or take it out of reset, every processor in the CPU complex
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* except the master (CPU 0) will be held in reset because the
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* AVP only talks to the master. The AVP does not know that there
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* are multiple processors in the CPU complex.
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*/
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int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
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int num_cpus = get_num_cpus();
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int cpu;
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debug("%s entry\n", __func__);
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/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
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for (cpu = 1; cpu < num_cpus; cpu++)
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reset_cmplx_set_enable(cpu, mask, 1);
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reset_cmplx_set_enable(0, mask, reset);
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/* Enable/Disable master CPU reset */
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reset_set_enable(PERIPH_ID_CPU, reset);
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}
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void clock_enable_coresight(int enable)
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{
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u32 rst, src = 2;
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debug("%s entry\n", __func__);
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clock_set_enable(PERIPH_ID_CORESIGHT, enable);
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reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
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if (enable) {
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/*
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* Put CoreSight on PLLP_OUT0 and divide it down as per
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* PLLP base frequency based on SoC type (T20/T30+).
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* Clock divider request would setup CSITE clock as 144MHz
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* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
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*/
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
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clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
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/* Unlock the CPU CoreSight interfaces */
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rst = CORESIGHT_UNLOCK;
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writel(rst, CSITE_CPU_DBG0_LAR);
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writel(rst, CSITE_CPU_DBG1_LAR);
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if (get_num_cpus() == 4) {
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writel(rst, CSITE_CPU_DBG2_LAR);
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writel(rst, CSITE_CPU_DBG3_LAR);
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}
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}
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}
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void halt_avp(void)
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{
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debug("%s entry\n", __func__);
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for (;;) {
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writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
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FLOW_CTLR_HALT_COP_EVENTS);
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}
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}
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