upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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81 lines
1.8 KiB
81 lines
1.8 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ath79.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ddr.h>
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#include <debug_uart.h>
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#ifdef CONFIG_USB
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static void wdr4300_usb_start(void)
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{
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void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
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AR71XX_GPIO_SIZE, MAP_NOCACHE);
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if (!gpio_regs)
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return;
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/* Power up the USB HUB. */
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clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
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writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
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mdelay(1);
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ath79_usb_reset();
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}
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#else
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static inline void wdr4300_usb_start(void) {}
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#endif
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void wdr4300_pinmux_config(void)
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{
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void __iomem *regs;
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regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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MAP_NOCACHE);
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/* Assure JTAG is not disconnected. */
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writel(0x40, regs + AR934X_GPIO_REG_FUNC);
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/* Configure default GPIO input/output regs. */
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writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
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writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
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/* Configure pin multiplexing. */
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writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
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writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
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writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
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writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
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writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
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writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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wdr4300_pinmux_config();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifndef CONFIG_DEBUG_UART_BOARD_INIT
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wdr4300_pinmux_config();
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#endif
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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ar934x_pll_init(560, 480, 240);
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ar934x_ddr_init(560, 480, 240);
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#endif
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wdr4300_usb_start();
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ath79_eth_reset();
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return 0;
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}
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#endif
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