upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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287 lines
6.5 KiB
287 lines
6.5 KiB
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <clps7111.h>
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#include <asm/proc-armv/ptrace.h>
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#include <asm/hardware.h>
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#ifndef CONFIG_NETARM
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/* we always count down the max. */
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#define TIMER_LOAD_VAL 0xffff
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/* macro to read the 16 bit timer */
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#define READ_TIMER (IO_TC1D & 0xffff)
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#ifdef CONFIG_LPC2292
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#undef READ_TIMER
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#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
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#endif
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#else
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#define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
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#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
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#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
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#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
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#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
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#endif
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#ifdef CONFIG_S3C4510B
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/* require interrupts for the S3C4510B */
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# ifndef CONFIG_USE_IRQ
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# error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
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# else
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static struct _irq_handler IRQ_HANDLER[N_IRQS];
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# endif
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#endif /* CONFIG_S3C4510B */
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#ifdef CONFIG_USE_IRQ
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void do_irq (struct pt_regs *pt_regs)
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{
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#if defined(CONFIG_S3C4510B)
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unsigned int pending;
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while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
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IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
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/* clear pending interrupt */
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PUT_REG( REG_INTPEND, (1<<(pending>>2)));
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}
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No do_irq() for IntegratorAP/CM720T as yet */
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#elif defined(CONFIG_LPC2292)
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void (*pfnct)(void);
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pfnct = (void (*)(void))VICVectAddr;
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(*pfnct)();
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#else
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#error do_irq() not defined for this CPU type
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#endif
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}
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#endif
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#ifdef CONFIG_S3C4510B
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static void default_isr( void *data) {
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printf ("default_isr(): called for IRQ %d\n", (int)data);
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}
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static void timer_isr( void *data) {
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unsigned int *pTime = (unsigned int *)data;
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(*pTime)++;
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if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
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/* toggle LED 0 */
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PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
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}
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}
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#endif
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#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* Use IntegratorAP routines in board/integratorap.c */
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#else
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static ulong timestamp;
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static ulong lastdec;
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#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
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int arch_interrupt_init (void)
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{
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int i;
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/* install default interrupt handlers */
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for ( i = 0; i < N_IRQS; i++) {
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IRQ_HANDLER[i].m_data = (void *)i;
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IRQ_HANDLER[i].m_func = default_isr;
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}
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/* configure interrupts for IRQ mode */
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PUT_REG( REG_INTMODE, 0x0);
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/* clear any pending interrupts */
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PUT_REG( REG_INTPEND, 0x1FFFFF);
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lastdec = 0;
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/* install interrupt handler for timer */
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IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
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IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
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return 0;
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}
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#endif
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int timer_init (void)
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{
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#if defined(CONFIG_NETARM)
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/* disable all interrupts */
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IRQEN = 0;
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/* operate timer 2 in non-prescale mode */
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TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
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NETARM_GEN_TCTL_ENABLE |
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NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
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/* set timer 2 counter */
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lastdec = TIMER_LOAD_VAL;
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#elif defined(CONFIG_S3C4510B)
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/* configure free running timer 0 */
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PUT_REG( REG_TMOD, 0x0);
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/* Stop timer 0 */
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CLR_REG( REG_TMOD, TM0_RUN);
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/* Configure for interval mode */
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CLR_REG( REG_TMOD, TM1_TOGGLE);
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/*
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* Load Timer data register with count down value.
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* count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
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*/
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PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
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/*
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* Enable global interrupt
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* Enable timer0 interrupt
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*/
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CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
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/* Start timer */
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SET_REG( REG_TMOD, TM0_RUN);
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#elif defined(CONFIG_LPC2292)
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PUT32(T0IR, 0); /* disable all timer0 interrupts */
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PUT32(T0TCR, 0); /* disable timer0 */
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PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
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PUT32(T0MCR, 0);
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PUT32(T0TC, 0);
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PUT32(T0TCR, 1); /* enable timer0 */
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#else
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#error No timer_init() defined for this CPU type
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#endif
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timestamp = 0;
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return (0);
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}
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#endif /* ! IntegratorAP */
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/*
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* timer without interrupts
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*/
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#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292)
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ulong get_timer (ulong base)
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{
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return get_timer_masked () - base;
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}
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void __udelay (unsigned long usec)
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{
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ulong tmo;
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tmo = usec / 1000;
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tmo *= CONFIG_SYS_HZ;
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tmo /= 1000;
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tmo += get_timer (0);
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while (get_timer_masked () < tmo)
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#ifdef CONFIG_LPC2292
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/* GJ - not sure whether this is really needed or a misunderstanding */
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__asm__ __volatile__(" nop");
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#else
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/*NOP*/;
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#endif
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}
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ulong get_timer_masked (void)
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{
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ulong now = READ_TIMER;
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if (lastdec >= now) {
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/* normal mode */
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timestamp += lastdec - now;
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} else {
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/* we have an overflow ... */
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timestamp += lastdec + TIMER_LOAD_VAL - now;
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}
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lastdec = now;
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return timestamp;
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}
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void udelay_masked (unsigned long usec)
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{
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ulong tmo;
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ulong endtime;
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signed long diff;
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= CONFIG_SYS_HZ;
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tmo /= 1000;
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} else {
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tmo = usec * CONFIG_SYS_HZ;
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tmo /= (1000*1000);
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}
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endtime = get_timer_masked () + tmo;
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do {
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ulong now = get_timer_masked ();
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diff = endtime - now;
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} while (diff >= 0);
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}
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#elif defined(CONFIG_S3C4510B)
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ulong get_timer (ulong base)
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{
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return timestamp - base;
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}
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void __udelay (unsigned long usec)
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{
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u32 ticks;
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ticks = (usec * CONFIG_SYS_HZ) / 1000000;
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ticks += get_timer (0);
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while (get_timer (0) < ticks)
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/*NOP*/;
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}
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#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
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/* No timer routines for IntegratorAP/CM720T as yet */
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#else
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#error Timer routines not defined for this CPU type
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#endif
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