upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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102 lines
2.6 KiB
102 lines
2.6 KiB
/*
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*
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* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined (CONFIG_IMX)
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#include <asm/arch/imx-regs.h>
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/* ------------------------------------------------------------------------- */
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/* NOTE: This describes the proper use of this file.
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*
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* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
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* SH FIXME: 16780000 in our case
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* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
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* the specified bus in HZ.
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*/
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/* ------------------------------------------------------------------------- */
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ulong get_systemPLLCLK(void)
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{
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/* FIXME: We assume System_SEL = 0 here */
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u32 spctl0 = SPCTL0;
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u32 mfi = (spctl0 >> 10) & 0xf;
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u32 mfn = spctl0 & 0x3f;
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u32 mfd = (spctl0 >> 16) & 0x3f;
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u32 pd = (spctl0 >> 26) & 0xf;
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mfi = mfi<=5 ? 5 : mfi;
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return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
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}
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ulong get_mcuPLLCLK(void)
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{
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/* FIXME: We assume System_SEL = 0 here */
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u32 mpctl0 = MPCTL0;
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u32 mfi = (mpctl0 >> 10) & 0xf;
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u32 mfn = mpctl0 & 0x3f;
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u32 mfd = (mpctl0 >> 16) & 0x3f;
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u32 pd = (mpctl0 >> 26) & 0xf;
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mfi = mfi<=5 ? 5 : mfi;
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return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
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}
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ulong get_FCLK(void)
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{
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return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK();
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}
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/* return HCLK frequency */
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ulong get_HCLK(void)
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{
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u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
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printf("bclkdiv: %d\n", bclkdiv);
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return get_systemPLLCLK() / bclkdiv;
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}
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/* return BCLK frequency */
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ulong get_BCLK(void)
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{
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return get_HCLK();
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}
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ulong get_PERCLK1(void)
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{
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return get_systemPLLCLK() / (((PCDR) & 0xf)+1);
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}
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ulong get_PERCLK2(void)
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{
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return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1);
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}
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ulong get_PERCLK3(void)
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{
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return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1);
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}
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#endif /* defined (CONFIG_IMX) */
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