upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
110 lines
2.2 KiB
110 lines
2.2 KiB
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* board/renesas/eagle/eagle.c
|
|
* This file is Eagle board support.
|
|
*
|
|
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <malloc.h>
|
|
#include <netdev.h>
|
|
#include <dm.h>
|
|
#include <dm/platform_data/serial_sh.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/mach-types.h>
|
|
#include <asm/io.h>
|
|
#include <linux/errno.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/gpio.h>
|
|
#include <asm/arch/gpio.h>
|
|
#include <asm/arch/rmobile.h>
|
|
#include <asm/arch/rcar-mstp.h>
|
|
#include <asm/arch/sh_sdhi.h>
|
|
#include <i2c.h>
|
|
#include <mmc.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define CPGWPR 0xE6150900
|
|
#define CPGWPCR 0xE6150904
|
|
|
|
/* PLL */
|
|
#define PLL0CR 0xE61500D8
|
|
#define PLL0_STC_MASK 0x7F000000
|
|
#define PLL0_STC_OFFSET 24
|
|
|
|
#define CLK2MHZ(clk) (clk / 1000 / 1000)
|
|
void s_init(void)
|
|
{
|
|
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
|
|
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
|
|
u32 stc;
|
|
|
|
/* Watchdog init */
|
|
writel(0xA5A5A500, &rwdt->rwtcsra);
|
|
writel(0xA5A5A500, &swdt->swtcsra);
|
|
|
|
/* CPU frequency setting. Set to 0.8GHz */
|
|
stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
|
|
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
|
|
}
|
|
|
|
#define TMU0_MSTP125 BIT(25) /* secure */
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
/* Unlock CPG access */
|
|
writel(0xA5A5FFFF, CPGWPR);
|
|
writel(0x5A5A0000, CPGWPCR);
|
|
|
|
/* TMU0 */
|
|
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* adress of boot parameters */
|
|
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
if (fdtdec_setup_mem_size_base() != 0)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init_banksize(void)
|
|
{
|
|
fdtdec_setup_memory_banksize();
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define RST_BASE 0xE6160000
|
|
#define RST_CA57RESCNT (RST_BASE + 0x40)
|
|
#define RST_CA53RESCNT (RST_BASE + 0x44)
|
|
#define RST_RSTOUTCR (RST_BASE + 0x58)
|
|
#define RST_CA57_CODE 0xA5A5000F
|
|
#define RST_CA53_CODE 0x5A5A000F
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
unsigned long midr, cputype;
|
|
|
|
asm volatile("mrs %0, midr_el1" : "=r" (midr));
|
|
cputype = (midr >> 4) & 0xfff;
|
|
|
|
if (cputype == 0xd03)
|
|
writel(RST_CA53_CODE, RST_CA53RESCNT);
|
|
else if (cputype == 0xd07)
|
|
writel(RST_CA57_CODE, RST_CA57RESCNT);
|
|
else
|
|
hang();
|
|
}
|
|
|