upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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128 lines
3.7 KiB
128 lines
3.7 KiB
/*
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* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/arch/orion5x.h>
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#include "edminiv2.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
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* which CFI does not properly detect, hence the LEGACY config.
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*/
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#if defined(CONFIG_FLASH_CFI_LEGACY)
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#include <flash.h>
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
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int sect;
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if (base != CONFIG_SYS_FLASH_BASE)
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return 0;
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info->size = 0;
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info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
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/* set each sector's start address and size based */
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for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
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info->start[sect] = base+info->size;
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info->size += sectsz[sect];
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}
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/* This flash must be accessed in 8-bits mode, no buffer. */
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info->flash_id = 0x01000000;
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info->portwidth = FLASH_CFI_8BIT;
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info->chipwidth = FLASH_CFI_BY8;
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info->buffer_size = 0;
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/* timings are derived from the Macronix datasheet. */
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info->erase_blk_tout = 1000;
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info->write_tout = 10;
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info->buffer_write_tout = 300;
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/* Commands and addresses are for AMD mode 8-bit access. */
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info->vendor = CFI_CMDSET_AMD_LEGACY;
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info->cmd_reset = 0xF0;
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info->interface = FLASH_CFI_X8;
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info->legacy_unlock = 0;
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info->ext_addr = 0;
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info->addr_unlock1 = 0x00000aaa;
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info->addr_unlock2 = 0x00000555;
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/* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
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info->manufacturer_id = 0x22;
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info->device_id = 0xBA;
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info->device_id2 = 0;
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info->cfi_version = 0x3133;
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info->cfi_offset = 0x0000;
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info->name = "MX29LV400CB";
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return 1;
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}
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#endif /* CONFIG_SYS_FLASH_CFI */
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int board_init(void)
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{
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/* arch number of board */
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gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
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/* boot parameter start at 256th byte of RAM base */
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gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
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return 0;
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}
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
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/* Configure and enable MV88E1116 PHY */
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void reset_phy(void)
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{
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u16 reg;
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u16 devadr;
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..%s could not read PHY dev address\n",
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__func__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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miiphy_reset(name, devadr);
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printf("88E1116 Initialized on %s\n", name);
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}
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#endif /* CONFIG_RESET_PHY_R */
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