upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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263 lines
6.8 KiB
263 lines
6.8 KiB
/*
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* Driver for Blackfin on-chip SDH controller
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*
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* Copyright (c) 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <part.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/byteorder.h>
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#include <asm/blackfin.h>
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#include <asm/portmux.h>
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#include <asm/mach-common/bits/sdh.h>
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#include <asm/mach-common/bits/dma.h>
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#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
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# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
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# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
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# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
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# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
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# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
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# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
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# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
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# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
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# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
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# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
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# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
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# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
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# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
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# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
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# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
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# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
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# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
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# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
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# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
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# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
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# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
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# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
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# define PORTMUX_PINS \
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{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
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#elif defined(__ADSPBF54x__)
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# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
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# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
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# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
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# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
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# define PORTMUX_PINS \
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{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
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#else
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# error no support for this proc yet
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#endif
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static int
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sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
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{
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unsigned int status, timeout;
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int cmd = mmc_cmd->cmdidx;
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int flags = mmc_cmd->resp_type;
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int arg = mmc_cmd->cmdarg;
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int ret;
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u16 sdh_cmd;
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sdh_cmd = cmd | CMD_E;
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if (flags & MMC_RSP_PRESENT)
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sdh_cmd |= CMD_RSP;
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if (flags & MMC_RSP_136)
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sdh_cmd |= CMD_L_RSP;
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bfin_write_SDH_ARGUMENT(arg);
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bfin_write_SDH_COMMAND(sdh_cmd);
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/* wait for a while */
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timeout = 0;
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do {
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if (++timeout > 1000000) {
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status = CMD_TIME_OUT;
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break;
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}
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udelay(1);
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status = bfin_read_SDH_STATUS();
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} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
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CMD_CRC_FAIL)));
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if (flags & MMC_RSP_PRESENT) {
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mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
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if (flags & MMC_RSP_136) {
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mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
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mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
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mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
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}
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}
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if (status & CMD_TIME_OUT)
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ret = TIMEOUT;
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else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
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ret = COMM_ERR;
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else
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ret = 0;
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bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
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CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
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return ret;
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}
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/* set data for single block transfer */
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static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
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{
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u16 data_ctl = 0;
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u16 dma_cfg = 0;
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int ret = 0;
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unsigned long data_size = data->blocksize * data->blocks;
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/* Don't support write yet. */
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if (data->flags & MMC_DATA_WRITE)
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return UNUSABLE_ERR;
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data_ctl |= ((ffs(data_size) - 1) << 4);
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data_ctl |= DTX_DIR;
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bfin_write_SDH_DATA_CTL(data_ctl);
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dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
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bfin_write_SDH_DATA_TIMER(-1);
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blackfin_dcache_flush_invalidate_range(data->dest,
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data->dest + data_size);
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/* configure DMA */
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bfin_write_DMA_START_ADDR(data->dest);
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bfin_write_DMA_X_COUNT(data_size / 4);
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bfin_write_DMA_X_MODIFY(4);
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bfin_write_DMA_CONFIG(dma_cfg);
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bfin_write_SDH_DATA_LGTH(data_size);
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/* kick off transfer */
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bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
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return ret;
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}
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static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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u32 status;
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int ret = 0;
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ret = sdh_send_cmd(mmc, cmd);
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if (ret) {
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printf("sending CMD%d failed\n", cmd->cmdidx);
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return ret;
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}
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if (data) {
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ret = sdh_setup_data(mmc, data);
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do {
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udelay(1);
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status = bfin_read_SDH_STATUS();
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} while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
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if (status & DAT_TIME_OUT) {
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bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
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ret |= TIMEOUT;
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} else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
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bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
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ret |= COMM_ERR;
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} else
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bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
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if (ret) {
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printf("tranfering data failed\n");
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return ret;
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}
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}
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return 0;
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}
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static void sdh_set_clk(unsigned long clk)
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{
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unsigned long sys_clk;
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unsigned long clk_div;
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u16 clk_ctl = 0;
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clk_ctl = bfin_read_SDH_CLK_CTL();
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if (clk) {
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/* setting SD_CLK */
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sys_clk = get_sclk();
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bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
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if (sys_clk % (2 * clk) == 0)
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clk_div = sys_clk / (2 * clk) - 1;
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else
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clk_div = sys_clk / (2 * clk);
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if (clk_div > 0xff)
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clk_div = 0xff;
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clk_ctl |= (clk_div & 0xff);
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clk_ctl |= CLK_E;
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bfin_write_SDH_CLK_CTL(clk_ctl);
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} else
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bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
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}
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static void bfin_sdh_set_ios(struct mmc *mmc)
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{
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u16 cfg = 0;
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u16 clk_ctl = 0;
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if (mmc->bus_width == 4) {
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cfg = bfin_read_SDH_CFG();
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cfg &= ~0x80;
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cfg |= 0x40;
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bfin_write_SDH_CFG(cfg);
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clk_ctl |= WIDE_BUS;
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}
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bfin_write_SDH_CLK_CTL(clk_ctl);
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sdh_set_clk(mmc->clock);
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}
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static int bfin_sdh_init(struct mmc *mmc)
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{
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const unsigned short pins[] = PORTMUX_PINS;
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u16 pwr_ctl = 0;
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/* Initialize sdh controller */
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peripheral_request_list(pins, "bfin_sdh");
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#if defined(__ADSPBF54x__)
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bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
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#endif
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bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
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/* Disable card detect pin */
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bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
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pwr_ctl |= ROD_CTL;
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pwr_ctl |= PWR_ON;
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bfin_write_SDH_PWR_CTL(pwr_ctl);
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return 0;
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}
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int bfin_mmc_init(bd_t *bis)
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{
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struct mmc *mmc = NULL;
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mmc = malloc(sizeof(struct mmc));
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if (!mmc)
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return -ENOMEM;
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sprintf(mmc->name, "Blackfin SDH");
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mmc->send_cmd = bfin_sdh_request;
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mmc->set_ios = bfin_sdh_set_ios;
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mmc->init = bfin_sdh_init;
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mmc->host_caps = MMC_MODE_4BIT;
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mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
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mmc->f_max = get_sclk();
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mmc->f_min = mmc->f_max >> 9;
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mmc->block_dev.part_type = PART_TYPE_DOS;
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mmc_register(mmc);
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return 0;
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}
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