upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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57 lines
1.4 KiB
57 lines
1.4 KiB
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include "fsl_epu.h"
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/**
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* fsl_epu_clean - Clear EPU registers
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*/
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void fsl_epu_clean(void *epu_base)
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{
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u32 offset;
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/* follow the exact sequence to clear the registers */
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/* Clear EPACRn */
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for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
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out_be32(epu_base + offset, 0);
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/* Clear EPEVTCRn */
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for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
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out_be32(epu_base + offset, 0);
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/* Clear EPGCR */
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out_be32(epu_base + EPGCR, 0);
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/* Clear EPSMCRn */
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for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
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out_be32(epu_base + offset, 0);
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/* Clear EPCCRn */
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for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
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out_be32(epu_base + offset, 0);
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/* Clear EPCMPRn */
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for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
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out_be32(epu_base + offset, 0);
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/* Clear EPCTRn */
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for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
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out_be32(epu_base + offset, 0);
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/* Clear EPIMCRn */
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for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
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out_be32(epu_base + offset, 0);
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/* Clear EPXTRIGCRn */
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out_be32(epu_base + EPXTRIGCR, 0);
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/* Clear EPECRn */
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for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
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out_be32(epu_base + offset, 0);
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}
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