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Peter Tyser
a1c8a71926
86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output
== Before ==
Freescale PowerPC
CPU:
Core: E600 Core 0, Version: 0.2, (0x80040202)
System: Unknown, Version: 2.1, (0x80900121)
Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC
== After ==
CPU: 8641D, Version: 2.1, (0x80900121)
Core: E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
CPU:1066.667 MHz, MPX:533.333 MHz
DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1: D-cache 32 KB enabled
I-cache 32 KB enabled
L2: 512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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16 years ago |
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4xx_pci.h
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4xx_pcie.h
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5xx_immap.h
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8xx_immap.h
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atomic.h
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bitops.h
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byteorder.h
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cache.h
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config.h
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cpm_85xx.h
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cpm_8260.h
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e300.h
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errno.h
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fsl_ddr_dimm_params.h
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fsl_ddr_sdram.h
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fsl_i2c.h
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fsl_law.h
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fsl_lbc.h
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fsl_serdes.h
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global_data.h
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gpio.h
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immap_83xx.h
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immap_85xx.h
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immap_86xx.h
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immap_512x.h
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immap_8220.h
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immap_8260.h
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immap_fsl_pci.h
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immap_qe.h
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interrupt.h
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io.h
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iopin_8xx.h
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iopin_85xx.h
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iopin_8260.h
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m8260_pci.h
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mc146818rtc.h
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mmu.h
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mpc8xxx_spi.h
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mpc8349_pci.h
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pci_io.h
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pnp.h
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posix_types.h
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ppc4xx-ebc.h
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ppc4xx-isram.h
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ppc4xx-sdram.h
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ppc4xx-uic.h
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processor.h
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ptrace.h
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residual.h
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sigcontext.h
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signal.h
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status_led.h
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string.h
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types.h
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u-boot.h
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xilinx_irq.h
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