upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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288 lines
7.7 KiB
288 lines
7.7 KiB
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2008 - 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <pci.h>
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#include <libfdt.h>
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#include "../common/common.h"
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* port pin dir open_drain assign */
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#if defined(CONFIG_KMETER1)
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/* MDIO */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 2, 1, 0, 1}, /* MDC */
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/* UCC4 - UEC */
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{1, 14, 1, 0, 1}, /* TxD0 */
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{1, 15, 1, 0, 1}, /* TxD1 */
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{1, 20, 2, 0, 1}, /* RxD0 */
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{1, 21, 2, 0, 1}, /* RxD1 */
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{1, 18, 1, 0, 1}, /* TX_EN */
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{1, 26, 2, 0, 1}, /* RX_DV */
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{1, 27, 2, 0, 1}, /* RX_ER */
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{1, 24, 2, 0, 1}, /* COL */
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{1, 25, 2, 0, 1}, /* CRS */
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{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
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{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
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/* DUART - UART2 */
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{5, 0, 1, 0, 2}, /* UART2_SOUT */
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{5, 2, 1, 0, 1}, /* UART2_RTS */
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{5, 3, 2, 0, 2}, /* UART2_SIN */
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{5, 1, 2, 0, 3}, /* UART2_CTS */
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#else
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/* Local Bus */
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{0, 16, 1, 0, 3}, /* LA00 */
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{0, 17, 1, 0, 3}, /* LA01 */
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{0, 18, 1, 0, 3}, /* LA02 */
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{0, 19, 1, 0, 3}, /* LA03 */
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{0, 20, 1, 0, 3}, /* LA04 */
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{0, 21, 1, 0, 3}, /* LA05 */
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{0, 22, 1, 0, 3}, /* LA06 */
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{0, 23, 1, 0, 3}, /* LA07 */
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{0, 24, 1, 0, 3}, /* LA08 */
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{0, 25, 1, 0, 3}, /* LA09 */
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{0, 26, 1, 0, 3}, /* LA10 */
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{0, 27, 1, 0, 3}, /* LA11 */
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{0, 28, 1, 0, 3}, /* LA12 */
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{0, 29, 1, 0, 3}, /* LA13 */
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{0, 30, 1, 0, 3}, /* LA14 */
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{0, 31, 1, 0, 3}, /* LA15 */
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/* MDIO */
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{3, 4, 3, 0, 2}, /* MDIO */
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{3, 5, 1, 0, 2}, /* MDC */
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/* UCC4 - UEC */
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{1, 18, 1, 0, 1}, /* TxD0 */
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{1, 19, 1, 0, 1}, /* TxD1 */
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{1, 22, 2, 0, 1}, /* RxD0 */
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{1, 23, 2, 0, 1}, /* RxD1 */
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{1, 26, 2, 0, 1}, /* RxER */
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{1, 28, 2, 0, 1}, /* Rx_DV */
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{1, 30, 1, 0, 1}, /* TxEN */
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{1, 31, 2, 0, 1}, /* CRS */
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{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
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#endif
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/* END of table */
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{0, 0, 0, 0, QE_IOP_TAB_END},
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};
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static int board_init_i2c_busses(void)
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{
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I2C_MUX_DEVICE *dev = NULL;
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uchar *buf;
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/* Set up the Bus for the DTTs */
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buf = (unsigned char *) getenv("dtt_bus");
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if (buf != NULL)
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dev = i2c_mux_ident_muxstring(buf);
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if (dev == NULL) {
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printf("Error couldn't add Bus for DTT\n");
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printf("please setup dtt_bus to where your\n");
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printf("DTT is found.\n");
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}
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return 0;
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}
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#if defined(CONFIG_SUVD3)
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const uint upma_table[] = {
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0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
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0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
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0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
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0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
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0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
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};
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#endif
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int board_early_init_r(void)
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{
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struct km_bec_fpga *base =
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(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
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#if defined(CONFIG_SUVD3)
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immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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fsl_lbc_t *lbc = &immap->im_lbc;
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u32 *mxmr = &lbc->mamr;
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#endif
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#if defined(CONFIG_MPC8360)
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unsigned short svid;
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/*
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* Because of errata in the UCCs, we have to write to the reserved
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* registers to slow the clocks down.
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*/
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svid = SVR_REV(mfspr(SVR));
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switch (svid) {
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case 0x0020:
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/*
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* MPC8360ECE.pdf QE_ENET10 table 4:
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* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
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* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
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*/
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setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
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break;
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case 0x0021:
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/*
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* MPC8360ECE.pdf QE_ENET10 table 4:
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* IMMR + 0x14AC[24:27] = 1010
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*/
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clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
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0x00000050, 0x000000a0);
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break;
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}
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#endif
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/* enable the PHY on the PIGGY */
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setbits_8(&base->pgy_eth, 0x01);
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/* enable the Unit LED (green) */
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setbits_8(&base->oprth, WRL_BOOT);
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#if defined(CONFIG_SUVD3)
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/* configure UPMA for APP1 */
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upmconfig(UPMA, (uint *) upma_table,
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sizeof(upma_table) / sizeof(uint));
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out_be32(mxmr, CONFIG_SYS_MAMR);
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#endif
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return 0;
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}
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int misc_init_r(void)
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{
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/* add board specific i2c busses */
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board_init_i2c_busses();
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return 0;
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}
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int last_stage_init(void)
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{
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set_km_env();
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return 0;
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}
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int fixed_sdram(void)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
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out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
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out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
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out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
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out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
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out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
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out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
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udelay(200);
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setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
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msize = CONFIG_SYS_DDR_SIZE << 20;
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disable_addr_trans();
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msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
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enable_addr_trans();
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msize /= (1024 * 1024);
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if (CONFIG_SYS_DDR_SIZE != msize) {
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size >> 1, ddr_size_log2++)
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if (ddr_size & 1)
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return -1;
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out_be32(&im->sysconf.ddrlaw[0].ar,
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(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
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out_be32(&im->ddr.csbnds[0].csbnds,
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(((msize / 16) - 1) & 0xff));
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}
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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out_be32(&im->sysconf.ddrlaw[0].bar,
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CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
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msize = fixed_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize DDR ECC byte
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus SDRAM size(bytes) -- DDR */
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return msize * 1024 * 1024;
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}
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int checkboard(void)
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{
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puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
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if (ethernet_present())
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puts(" with PIGGY.");
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puts("\n");
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif
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#if defined(CONFIG_HUSH_INIT_VAR)
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int hush_init_var(void)
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{
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ivm_read_eeprom();
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return 0;
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}
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#endif
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