upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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369 lines
10 KiB
369 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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* (C) Copyright 2012 Renesas Solutions Corp.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <netdev.h>
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#include <i2c.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CS0BCR_D (0x06C00400)
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#define CS4BCR_D (0x16c90400)
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#define CS0WCR_D (0x55062C42)
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#define CS4WCR_D (0x1e071dc3)
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#define CMNCR_BROMMD0 (1 << 21)
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#define CMNCR_BROMMD1 (1 << 22)
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#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
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#define VCLKCR1_D (0x27)
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#define SMSTPCR1_CMT0 (1 << 24)
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#define SMSTPCR1_I2C0 (1 << 16)
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#define SMSTPCR3_USB (1 << 22)
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#define SMSTPCR3_I2C1 (1 << 23)
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#define PORT32CR (0xE6051020)
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#define PORT33CR (0xE6051021)
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#define PORT34CR (0xE6051022)
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#define PORT35CR (0xE6051023)
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static int cmp_loop(u32 *addr, u32 data, u32 cmp)
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{
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int err = -1;
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int timeout = 100;
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u32 value;
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while (timeout > 0) {
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value = readl(addr);
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if ((value & data) == cmp) {
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err = 0;
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break;
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}
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timeout--;
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}
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return err;
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}
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/* SBSC Init function */
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static void sbsc_init(struct sh73a0_sbsc *sbsc)
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{
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writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
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writel(0x5, &sbsc->sdgencnt);
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cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
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writel(0xacc90159, &sbsc->sdcr0);
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writel(0x00010059, &sbsc->sdcr1);
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writel(0x50874114, &sbsc->sdwcrc0);
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writel(0x33199b37, &sbsc->sdwcrc1);
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writel(0x008f2313, &sbsc->sdwcrc2);
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writel(0x31020707, &sbsc->sdwcr00);
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writel(0x0017040a, &sbsc->sdwcr01);
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writel(0x31020707, &sbsc->sdwcr10);
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writel(0x0017040a, &sbsc->sdwcr11);
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writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
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writel(0x30000000, &sbsc->sdwcr2);
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writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
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cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
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writel(0x00002710, &sbsc->sdgencnt);
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cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
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writel(0x0000003f, &sbsc->sdmracr0);
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writel(0x0, SDMRA1A);
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writel(0x000001f4, &sbsc->sdgencnt);
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cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
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writel(0x0000ff0a, &sbsc->sdmracr0);
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if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
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writel(0x0, SDMRA3A);
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else
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writel(0x0, SDMRA3B);
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writel(0x00000032, &sbsc->sdgencnt);
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cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
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if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
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writel(0x00002201, &sbsc->sdmracr0);
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writel(0x0, SDMRA1A);
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writel(0x00000402, &sbsc->sdmracr0);
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writel(0x0, SDMRA1A);
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writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
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writel(0x0, SDMRA1A);
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writel(0x0, SDMRA2A);
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} else {
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writel(0x00002201, &sbsc->sdmracr0);
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writel(0x0, SDMRA1B);
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writel(0x00000402, &sbsc->sdmracr0);
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writel(0x0, SDMRA1B);
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writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
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writel(0x0, SDMRA1B);
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writel(0x0, SDMRA2B);
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}
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writel(0x88800004, &sbsc->sdmrtmpcr);
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writel(0x00000004, &sbsc->sdmrtmpmsk);
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writel(0xa55a0032, &sbsc->rtcor);
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writel(0xa55a000c, &sbsc->rtcorh);
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writel(0xa55a2048, &sbsc->rtcsr);
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writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
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writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
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writel(0xfff20000, &sbsc->zqccr);
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/* SCBS2 only */
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if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
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writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
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writel(0xa5390000, &sbsc->dphycnt1);
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writel(0x00001200, &sbsc->dphycnt0);
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writel(0x07ce0000, &sbsc->dphycnt1);
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writel(0x00001247, &sbsc->dphycnt0);
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cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
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writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
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}
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}
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void s_init(void)
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{
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struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
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struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
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struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
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(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
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struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
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struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
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struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
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struct sh73a0_hpb_bscr *hpb_bscr =
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(struct sh73a0_hpb_bscr *)HPBSCR_BASE;
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/* Watchdog init */
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writew(0xA507, &rwdt->rwtcsra0);
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/* Secure control register Init */
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#define LIFEC_SEC_SRC_BIT (1 << 15)
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writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
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clrbits_le32(&cpg->smstpcr3, (1 << 15));
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clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
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clrbits_le32(&cpg->smstpcr2, (1 << 18));
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clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
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writel(0x0, &cpg->pllecr);
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cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
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cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
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writel(0x2D000000, &cpg->pll0cr);
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writel(0x17100000, &cpg->pll1cr);
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writel(0x96235880, &cpg->frqcrb);
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cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
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writel(0xB, &cpg->flckcr);
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clrbits_le32(&cpg->smstpcr0, (1 << 1));
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clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
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writel(0x0514, &hpb_bscr->smgpiotime);
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writel(0x0514, &hpb_bscr->smcmt2time);
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writel(0x0514, &hpb_bscr->smcpgtime);
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writel(0x0514, &hpb_bscr->smsysctime);
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writel(0x00092000, &cpg->dvfscr4);
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writel(0x000000DC, &cpg->dvfscr5);
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writel(0x0, &cpg->pllecr);
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cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
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/* FRQCR Init */
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writel(0x0012453C, &cpg->frqcra);
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writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */
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cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
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writel(0x00000B0B, &cpg->frqcrd);
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cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
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/* Clock Init */
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writel(0x00000003, PCLKCR);
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writel(0x0000012F, &cpg->vclkcr1);
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writel(0x00000119, &cpg->vclkcr2);
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writel(0x00000119, &cpg->vclkcr3);
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writel(0x00000002, &cpg->zbckcr);
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writel(0x00000005, &cpg->flckcr);
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writel(0x00000080, &cpg->sd0ckcr);
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writel(0x00000080, &cpg->sd1ckcr);
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writel(0x00000080, &cpg->sd2ckcr);
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writel(0x0000003F, &cpg->fsiackcr);
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writel(0x0000003F, &cpg->fsibckcr);
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writel(0x00000080, &cpg->subckcr);
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writel(0x0000000B, &cpg->spuackcr);
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writel(0x0000000B, &cpg->spuvckcr);
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writel(0x0000013F, &cpg->msuckcr);
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writel(0x00000080, &cpg->hsickcr);
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writel(0x0000003F, &cpg->mfck1cr);
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writel(0x0000003F, &cpg->mfck2cr);
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writel(0x00000107, &cpg->dsitckcr);
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writel(0x00000313, &cpg->dsi0pckcr);
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writel(0x0000130D, &cpg->dsi1pckcr);
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writel(0x2A800E0E, &cpg->dsi0phycr);
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writel(0x1E000000, &cpg->pll0cr);
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writel(0x2D000000, &cpg->pll0cr);
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writel(0x17100000, &cpg->pll1cr);
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writel(0x27000080, &cpg->pll2cr);
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writel(0x1D000000, &cpg->pll3cr);
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writel(0x00080000, &cpg->pll0stpcr);
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writel(0x000120C0, &cpg->pll1stpcr);
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writel(0x00012000, &cpg->pll2stpcr);
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writel(0x00000030, &cpg->pll3stpcr);
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writel(0x0000000B, &cpg->pllecr);
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cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
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writel(0x000120F0, &cpg->dvfscr3);
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writel(0x00000020, &cpg->mpmode);
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writel(0x0000028A, &cpg->vrefcr);
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writel(0xE4628087, &cpg->rmstpcr0);
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writel(0xFFFFFFFF, &cpg->rmstpcr1);
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writel(0x53FFFFFF, &cpg->rmstpcr2);
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writel(0xFFFFFFFF, &cpg->rmstpcr3);
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writel(0x00800D3D, &cpg->rmstpcr4);
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writel(0xFFFFF3FF, &cpg->rmstpcr5);
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writel(0x00000000, &cpg->smstpcr2);
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writel(0x00040000, &cpg_srcr->srcr2);
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clrbits_le32(&cpg->pllecr, (1 << 3));
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cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
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writel(0x00000001, &hpb->hpbctrl6);
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cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
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writel(0x00001414, &cpg->frqcrd);
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cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
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writel(0x1d000000, &cpg->pll3cr);
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setbits_le32(&cpg->pllecr, (1 << 3));
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cmp_loop(&cpg->pllecr, 0x800, 0x800);
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/* SBSC1 Init*/
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sbsc_init(sbsc1);
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/* SBSC2 Init*/
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sbsc_init(sbsc2);
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writel(0x00000b0b, &cpg->frqcrd);
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cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
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writel(0xfffffffc, &cpg->cpgxxcs4);
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}
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int board_early_init_f(void)
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{
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struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
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struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
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struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
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(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
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writel(CS0BCR_D, &bsc->cs0bcr);
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writel(CS4BCR_D, &bsc->cs4bcr);
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writel(CS0WCR_D, &bsc->cs0wcr);
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writel(CS4WCR_D, &bsc->cs4wcr);
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clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
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clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
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clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
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clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
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clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
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writel(VCLKCR1_D, &cpg->vclkcr1);
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/* Setup SCIF4 / workaround */
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writeb(0x12, PORT32CR);
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writeb(0x22, PORT33CR);
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writeb(0x12, PORT34CR);
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writeb(0x22, PORT35CR);
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return 0;
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}
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void adjust_core_voltage(void)
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{
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u8 data;
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data = 0x35;
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i2c_set_bus_num(0);
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i2c_write(0x40, 3, 1, &data, 1);
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}
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int board_init(void)
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{
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adjust_core_voltage();
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sh73a0_pinmux_init();
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/* SCIFA 4 */
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gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
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gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
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gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
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gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
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/* Ethernet/SMSC */
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gpio_request(GPIO_PORT224, NULL);
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gpio_direction_input(GPIO_PORT224);
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/* SMSC/USB */
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gpio_request(GPIO_FN_CS4_, NULL);
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/* MMCIF */
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gpio_request(GPIO_FN_MMCCLK0, NULL);
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gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
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gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
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/* SDHI */
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gpio_request(GPIO_FN_SDHIWP0, NULL);
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gpio_request(GPIO_FN_SDHICD0, NULL);
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gpio_request(GPIO_FN_SDHICMD0, NULL);
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gpio_request(GPIO_FN_SDHICLK0, NULL);
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gpio_request(GPIO_FN_SDHID0_3, NULL);
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gpio_request(GPIO_FN_SDHID0_2, NULL);
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gpio_request(GPIO_FN_SDHID0_1, NULL);
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gpio_request(GPIO_FN_SDHID0_0, NULL);
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gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
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gpio_request(GPIO_PORT15, NULL);
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gpio_direction_output(GPIO_PORT15, 1);
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/* I2C */
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gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
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gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
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gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
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gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
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gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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#ifdef CONFIG_SMC911X
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ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return ret;
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}
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void reset_cpu(ulong addr)
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{
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/* Soft Power On Reset */
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writel((1 << 31), RESCNT2);
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}
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