upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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250 lines
6.6 KiB
250 lines
6.6 KiB
/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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aliases {
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mmc1 = &usdhc3;
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};
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memory {
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reg = <0x10000000 0x80000000>;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_3p3v>;
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_3p3v>;
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
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phy-mode = "rmii";
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4>;
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status = "okay";
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};
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&usdhc1 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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no-1-8-v;
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non-removable;
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status = "disabled";
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};
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&iomuxc {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b1
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0
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MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
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MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
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MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
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>;
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};
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pinctrl_gpmi_nand: gpmi-nand {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
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MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
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MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
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MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
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>;
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};
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
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MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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u-boot,dm-spl;
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fsl,pins = <
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MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17070
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MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10070
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MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
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MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
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MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
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MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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u-boot,dm-spl;
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
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MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
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MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
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MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
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MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
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>;
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};
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};
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