upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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478 lines
11 KiB
478 lines
11 KiB
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <bootm.h>
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#include <common.h>
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#include <netdev.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <imx_thermal.h>
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#include <ipu_pixfmt.h>
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#include <thermal.h>
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#include <sata.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
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static u32 reset_cause = -1;
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static char *get_reset_cause(void)
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{
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u32 cause;
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struct src *src_regs = (struct src *)SRC_BASE_ADDR;
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cause = readl(&src_regs->srsr);
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writel(cause, &src_regs->srsr);
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reset_cause = cause;
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switch (cause) {
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case 0x00001:
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case 0x00011:
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return "POR";
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case 0x00004:
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return "CSU";
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case 0x00008:
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return "IPP USER";
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case 0x00010:
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#ifdef CONFIG_MX7
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return "WDOG1";
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#else
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return "WDOG";
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#endif
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case 0x00020:
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return "JTAG HIGH-Z";
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case 0x00040:
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return "JTAG SW";
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case 0x00080:
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return "WDOG3";
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#ifdef CONFIG_MX7
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case 0x00100:
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return "WDOG4";
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case 0x00200:
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return "TEMPSENSE";
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#elif defined(CONFIG_MX8M)
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case 0x00100:
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return "WDOG2";
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case 0x00200:
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return "TEMPSENSE";
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#else
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case 0x00100:
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return "TEMPSENSE";
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case 0x10000:
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return "WARM BOOT";
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#endif
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default:
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return "unknown reset";
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}
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}
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u32 get_imx_reset_cause(void)
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{
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return reset_cause;
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}
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#endif
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#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
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#if defined(CONFIG_MX53)
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#define MEMCTL_BASE ESDCTL_BASE_ADDR
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#else
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#define MEMCTL_BASE MMDC_P0_BASE_ADDR
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#endif
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static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
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static const unsigned char bank_lookup[] = {3, 2};
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/* these MMDC registers are common to the IMX53 and IMX6 */
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struct esd_mmdc_regs {
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uint32_t ctl;
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uint32_t pdc;
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uint32_t otc;
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uint32_t cfg0;
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uint32_t cfg1;
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uint32_t cfg2;
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uint32_t misc;
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};
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#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
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#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
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#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
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#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
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#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
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/*
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* imx_ddr_size - return size in bytes of DRAM according MMDC config
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* The MMDC MDCTL register holds the number of bits for row, col, and data
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* width and the MMDC MDMISC register holds the number of banks. Combine
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* all these bits to determine the meme size the MMDC has been configured for
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*/
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unsigned imx_ddr_size(void)
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{
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struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
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unsigned ctl = readl(&mem->ctl);
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unsigned misc = readl(&mem->misc);
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int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
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bits += ESD_MMDC_CTL_GET_ROW(ctl);
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bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
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bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
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bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
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bits += ESD_MMDC_CTL_GET_CS1(ctl);
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/* The MX6 can do only 3840 MiB of DRAM */
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if (bits == 32)
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return 0xf0000000;
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return 1 << bits;
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}
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
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const char *get_imx_type(u32 imxtype)
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{
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switch (imxtype) {
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case MXC_CPU_MX8MQ:
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return "8MQ"; /* Quad-core version of the mx8m */
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case MXC_CPU_MX7S:
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return "7S"; /* Single-core version of the mx7 */
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case MXC_CPU_MX7D:
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return "7D"; /* Dual-core version of the mx7 */
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case MXC_CPU_MX6QP:
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return "6QP"; /* Quad-Plus version of the mx6 */
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case MXC_CPU_MX6DP:
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return "6DP"; /* Dual-Plus version of the mx6 */
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case MXC_CPU_MX6Q:
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return "6Q"; /* Quad-core version of the mx6 */
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case MXC_CPU_MX6D:
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return "6D"; /* Dual-core version of the mx6 */
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case MXC_CPU_MX6DL:
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return "6DL"; /* Dual Lite version of the mx6 */
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case MXC_CPU_MX6SOLO:
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return "6SOLO"; /* Solo version of the mx6 */
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case MXC_CPU_MX6SL:
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return "6SL"; /* Solo-Lite version of the mx6 */
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case MXC_CPU_MX6SLL:
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return "6SLL"; /* SLL version of the mx6 */
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case MXC_CPU_MX6SX:
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return "6SX"; /* SoloX version of the mx6 */
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case MXC_CPU_MX6UL:
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return "6UL"; /* Ultra-Lite version of the mx6 */
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case MXC_CPU_MX6ULL:
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return "6ULL"; /* ULL version of the mx6 */
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case MXC_CPU_MX51:
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return "51";
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case MXC_CPU_MX53:
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return "53";
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default:
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return "??";
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}
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}
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int print_cpuinfo(void)
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{
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u32 cpurev;
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__maybe_unused u32 max_freq;
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cpurev = get_cpu_rev();
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#if defined(CONFIG_IMX_THERMAL)
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struct udevice *thermal_dev;
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int cpu_tmp, minc, maxc, ret;
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printf("CPU: Freescale i.MX%s rev%d.%d",
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get_imx_type((cpurev & 0xFF000) >> 12),
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(cpurev & 0x000F0) >> 4,
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(cpurev & 0x0000F) >> 0);
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max_freq = get_cpu_speed_grade_hz();
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if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
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printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
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} else {
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printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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}
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#else
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printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
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get_imx_type((cpurev & 0xFF000) >> 12),
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(cpurev & 0x000F0) >> 4,
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(cpurev & 0x0000F) >> 0,
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mxc_get_clock(MXC_ARM_CLK) / 1000000);
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#endif
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#if defined(CONFIG_IMX_THERMAL)
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puts("CPU: ");
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switch (get_cpu_temp_grade(&minc, &maxc)) {
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case TEMP_AUTOMOTIVE:
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puts("Automotive temperature grade ");
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break;
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case TEMP_INDUSTRIAL:
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puts("Industrial temperature grade ");
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break;
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case TEMP_EXTCOMMERCIAL:
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puts("Extended Commercial temperature grade ");
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break;
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default:
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puts("Commercial temperature grade ");
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break;
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}
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printf("(%dC to %dC)", minc, maxc);
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ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
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if (!ret) {
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ret = thermal_get_temp(thermal_dev, &cpu_tmp);
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if (!ret)
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printf(" at %dC\n", cpu_tmp);
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else
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debug(" - invalid sensor data\n");
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} else {
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debug(" - invalid sensor device\n");
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}
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#endif
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printf("Reset cause: %s\n", get_reset_cause());
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return 0;
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int rc = -ENODEV;
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#if defined(CONFIG_FEC_MXC)
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rc = fecmxc_initialize(bis);
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#endif
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return rc;
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}
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#ifdef CONFIG_FSL_ESDHC
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/*
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* Initializes on-chip MMC controllers.
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* to override, implement board_mmc_init()
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*/
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
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u32 get_ahb_clk(void)
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{
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struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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u32 reg, ahb_podf;
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reg = __raw_readl(&imx_ccm->cbcdr);
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reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
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ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
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return get_periph_clk() / (ahb_podf + 1);
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}
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#endif
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void arch_preboot_os(void)
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{
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#if defined(CONFIG_PCIE_IMX)
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imx_pcie_remove();
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#endif
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#if defined(CONFIG_SATA)
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sata_remove(0);
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#if defined(CONFIG_MX6)
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disable_sata_clock();
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#endif
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#endif
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#if defined(CONFIG_VIDEO_IPUV3)
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/* disable video before launching O/S */
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ipuv3_fb_shutdown();
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#endif
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#if defined(CONFIG_VIDEO_MXS)
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lcdif_power_down();
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#endif
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}
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#ifndef CONFIG_MX8M
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void set_chipselect_size(int const cs_size)
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{
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unsigned int reg;
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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reg = readl(&iomuxc_regs->gpr[1]);
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switch (cs_size) {
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case CS0_128:
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reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
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reg |= 0x5;
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break;
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case CS0_64M_CS1_64M:
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reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
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reg |= 0x1B;
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break;
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case CS0_64M_CS1_32M_CS2_32M:
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reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
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reg |= 0x4B;
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break;
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case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
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reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
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reg |= 0x249;
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break;
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default:
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printf("Unknown chip select size: %d\n", cs_size);
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break;
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}
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writel(reg, &iomuxc_regs->gpr[1]);
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}
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#endif
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#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
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/*
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* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
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* defines a 2-bit SPEED_GRADING
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*/
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#define OCOTP_TESTER3_SPEED_SHIFT 8
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enum cpu_speed {
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OCOTP_TESTER3_SPEED_GRADE0,
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OCOTP_TESTER3_SPEED_GRADE1,
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OCOTP_TESTER3_SPEED_GRADE2,
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OCOTP_TESTER3_SPEED_GRADE3,
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};
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u32 get_cpu_speed_grade_hz(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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uint32_t val;
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val = readl(&fuse->tester3);
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val >>= OCOTP_TESTER3_SPEED_SHIFT;
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val &= 0x3;
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switch(val) {
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case OCOTP_TESTER3_SPEED_GRADE0:
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return 800000000;
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case OCOTP_TESTER3_SPEED_GRADE1:
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return is_mx7() ? 500000000 : 1000000000;
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case OCOTP_TESTER3_SPEED_GRADE2:
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return is_mx7() ? 1000000000 : 1300000000;
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case OCOTP_TESTER3_SPEED_GRADE3:
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return is_mx7() ? 1200000000 : 1500000000;
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}
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return 0;
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}
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/*
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* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
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* defines a 2-bit SPEED_GRADING
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*/
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#define OCOTP_TESTER3_TEMP_SHIFT 6
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u32 get_cpu_temp_grade(int *minc, int *maxc)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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uint32_t val;
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val = readl(&fuse->tester3);
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val >>= OCOTP_TESTER3_TEMP_SHIFT;
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val &= 0x3;
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if (minc && maxc) {
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if (val == TEMP_AUTOMOTIVE) {
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*minc = -40;
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*maxc = 125;
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} else if (val == TEMP_INDUSTRIAL) {
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*minc = -40;
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*maxc = 105;
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} else if (val == TEMP_EXTCOMMERCIAL) {
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*minc = -20;
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*maxc = 105;
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} else {
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*minc = 0;
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*maxc = 95;
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}
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}
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return val;
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}
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#endif
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#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
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enum boot_device get_boot_device(void)
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{
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struct bootrom_sw_info **p =
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(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
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enum boot_device boot_dev = SD1_BOOT;
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u8 boot_type = (*p)->boot_dev_type;
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u8 boot_instance = (*p)->boot_dev_instance;
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switch (boot_type) {
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case BOOT_TYPE_SD:
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boot_dev = boot_instance + SD1_BOOT;
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break;
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case BOOT_TYPE_MMC:
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boot_dev = boot_instance + MMC1_BOOT;
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break;
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case BOOT_TYPE_NAND:
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boot_dev = NAND_BOOT;
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break;
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case BOOT_TYPE_QSPI:
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boot_dev = QSPI_BOOT;
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break;
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case BOOT_TYPE_WEIM:
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boot_dev = WEIM_NOR_BOOT;
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break;
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case BOOT_TYPE_SPINOR:
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boot_dev = SPI_NOR_BOOT;
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break;
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#ifdef CONFIG_MX8M
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case BOOT_TYPE_USB:
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boot_dev = USB_BOOT;
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break;
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#endif
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default:
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break;
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}
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return boot_dev;
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}
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#endif
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#ifdef CONFIG_NXP_BOARD_REVISION
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int nxp_board_rev(void)
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{
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/*
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* Get Board ID information from OCOTP_GP1[15:8]
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* RevA: 0x1
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* RevB: 0x2
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* RevC: 0x3
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*/
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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return (readl(&fuse->gp1) >> 8 & 0x0F);
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}
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char nxp_board_rev_string(void)
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{
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const char *rev = "A";
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return (*rev + nxp_board_rev() - 1);
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}
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#endif
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