upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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45 lines
1.2 KiB
45 lines
1.2 KiB
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#ifdef CONFIG_FSL_ESDHC
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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int get_clocks(void)
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{
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#ifdef CONFIG_FSL_ESDHC
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#ifdef CONFIG_FSL_USDHC
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#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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#else
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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#endif
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#else
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#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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#else
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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#endif
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#endif
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#endif
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return 0;
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}
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