upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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472 lines
13 KiB
472 lines
13 KiB
/*
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* Sun8i a33 platform dram controller init.
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*
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* (C) Copyright 2007-2015 Allwinner Technology Co.
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* Jerry Wang <wangflord@allwinnertech.com>
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/prcm.h>
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#define DRAM_CLK_MUL 2
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#define DRAM_CLK_DIV 1
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struct dram_para {
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u8 cs1;
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u8 seq;
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u8 bank;
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u8 rank;
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u8 rows;
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u8 bus_width;
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u8 dram_type;
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u16 page_size;
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};
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static void mctl_set_cr(struct dram_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
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MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |
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(para->seq ? MCTL_CR_SEQUENCE : 0) |
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((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
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MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
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MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
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&mctl_com->cr);
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}
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static void auto_detect_dram_size(struct dram_para *para)
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{
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u8 orig_rank = para->rank;
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int rows, columns;
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/* Row detect */
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para->page_size = 512;
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para->seq = 1;
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para->rows = 16;
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para->rank = 1;
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mctl_set_cr(para);
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for (rows = 11 ; rows < 16 ; rows++) {
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if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
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break;
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}
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/* Column (page size) detect */
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para->rows = 11;
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para->page_size = 8192;
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mctl_set_cr(para);
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for (columns = 9 ; columns < 13 ; columns++) {
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if (mctl_mem_matches(1 << columns))
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break;
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}
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para->seq = 0;
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para->rank = orig_rank;
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para->rows = rows;
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para->page_size = 1 << columns;
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mctl_set_cr(para);
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}
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static inline int ns_to_t(int nanoseconds)
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{
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const unsigned int ctrl_freq =
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CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
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return (ctrl_freq * nanoseconds + 999) / 1000;
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}
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static void auto_set_timing_para(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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u32 reg_val;
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u8 tccd = 2;
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u8 tfaw = ns_to_t(50);
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u8 trrd = max(ns_to_t(10), 4);
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u8 trcd = ns_to_t(15);
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u8 trc = ns_to_t(53);
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u8 txp = max(ns_to_t(8), 3);
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u8 twtr = max(ns_to_t(8), 4);
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u8 trtp = max(ns_to_t(8), 4);
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u8 twr = max(ns_to_t(15), 3);
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u8 trp = ns_to_t(15);
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u8 tras = ns_to_t(38);
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u16 trefi = ns_to_t(7800) / 32;
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u16 trfc = ns_to_t(350);
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/* Fixed timing parameters */
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u8 tmrw = 0;
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u8 tmrd = 4;
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u8 tmod = 12;
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u8 tcke = 3;
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u8 tcksrx = 5;
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u8 tcksre = 5;
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u8 tckesr = 4;
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u8 trasmax = 24;
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u8 tcl = 6; /* CL 12 */
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u8 tcwl = 4; /* CWL 8 */
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u8 t_rdata_en = 4;
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u8 wr_latency = 2;
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u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
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u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
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u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
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u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
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/* Set work mode register */
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mctl_set_cr(para);
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/* Set mode register */
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if (para->dram_type == DRAM_TYPE_DDR3) {
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writel(MCTL_MR0, &mctl_ctl->mr0);
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writel(MCTL_MR1, &mctl_ctl->mr1);
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writel(MCTL_MR2, &mctl_ctl->mr2);
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writel(MCTL_MR3, &mctl_ctl->mr3);
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} else if (para->dram_type == DRAM_TYPE_LPDDR3) {
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writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0);
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writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1);
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writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2);
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writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3);
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/* timing parameters for LPDDR3 */
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tfaw = max(ns_to_t(50), 4);
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trrd = max(ns_to_t(10), 2);
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trcd = max(ns_to_t(24), 2);
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trc = ns_to_t(70);
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txp = max(ns_to_t(8), 2);
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twtr = max(ns_to_t(8), 2);
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trtp = max(ns_to_t(8), 2);
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trp = max(ns_to_t(27), 2);
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tras = ns_to_t(42);
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trefi = ns_to_t(3900) / 32;
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trfc = ns_to_t(210);
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tmrw = 5;
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tmrd = 5;
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tckesr = 5;
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tcwl = 3; /* CWL 8 */
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t_rdata_en = 5;
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tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
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tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */
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tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 200us */
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tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */
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twr2rd = tcwl + 4 + 1 + twtr; /* WL + BL / 2 + tWTR */
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trd2wr = tcl + 4 + 5 - tcwl + 1; /* RL + BL / 2 + 2 - WL */
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}
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/* Set dram timing */
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reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
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writel(reg_val, &mctl_ctl->dramtmg0);
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reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
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writel(reg_val, &mctl_ctl->dramtmg1);
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reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
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writel(reg_val, &mctl_ctl->dramtmg2);
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reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
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writel(reg_val, &mctl_ctl->dramtmg3);
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reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
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writel(reg_val, &mctl_ctl->dramtmg4);
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reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
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writel(reg_val, &mctl_ctl->dramtmg5);
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/* Set two rank timing and exit self-refresh timing */
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reg_val = readl(&mctl_ctl->dramtmg8);
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reg_val &= ~(0xff << 8);
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reg_val &= ~(0xff << 0);
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reg_val |= (0x33 << 8);
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reg_val |= (0x8 << 0);
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writel(reg_val, &mctl_ctl->dramtmg8);
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/* Set phy interface time */
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reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
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| (wr_latency << 0);
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/* PHY interface write latency and read latency configure */
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writel(reg_val, &mctl_ctl->pitmg0);
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/* Set phy time PTR0-2 use default */
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writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
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writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
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/* Set refresh timing */
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reg_val = (trefi << 16) | (trfc << 0);
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writel(reg_val, &mctl_ctl->rfshtmg);
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}
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static void mctl_set_pir(u32 val)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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writel(val, &mctl_ctl->pir);
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mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
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}
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static void mctl_data_train_cfg(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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if (para->rank == 2)
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clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
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else
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clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
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}
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static int mctl_train_dram(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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mctl_data_train_cfg(para);
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mctl_set_pir(0x5f3);
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return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
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}
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static void set_master_priority(void)
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{
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writel(0x00a0000d, MCTL_MASTER_CFG0(0));
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writel(0x00500064, MCTL_MASTER_CFG1(0));
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writel(0x07000009, MCTL_MASTER_CFG0(1));
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writel(0x00000600, MCTL_MASTER_CFG1(1));
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writel(0x01000009, MCTL_MASTER_CFG0(3));
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writel(0x00000064, MCTL_MASTER_CFG1(3));
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writel(0x08000009, MCTL_MASTER_CFG0(4));
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writel(0x00000640, MCTL_MASTER_CFG1(4));
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writel(0x20000308, MCTL_MASTER_CFG0(8));
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writel(0x00001000, MCTL_MASTER_CFG1(8));
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writel(0x02800009, MCTL_MASTER_CFG0(9));
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writel(0x00000100, MCTL_MASTER_CFG1(9));
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writel(0x01800009, MCTL_MASTER_CFG0(5));
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writel(0x00000100, MCTL_MASTER_CFG1(5));
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writel(0x01800009, MCTL_MASTER_CFG0(7));
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writel(0x00000100, MCTL_MASTER_CFG1(7));
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writel(0x00640009, MCTL_MASTER_CFG0(6));
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writel(0x00000032, MCTL_MASTER_CFG1(6));
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writel(0x0100000d, MCTL_MASTER_CFG0(2));
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writel(0x00500080, MCTL_MASTER_CFG1(2));
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}
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static int mctl_channel_init(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
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u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
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u32 i, rval;
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auto_set_timing_para(para);
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/* Set dram master access priority */
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writel(0x000101a0, &mctl_com->bwcr);
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/* set cpu high priority */
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writel(0x1, &mctl_com->mapr);
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set_master_priority();
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udelay(250);
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/* Disable dram VTC */
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clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
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clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
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writel(0x94be6fa3, MCTL_PROTECT);
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udelay(100);
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clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 16);
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writel(0x0, MCTL_PROTECT);
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udelay(100);
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/* Set ODT */
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if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
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rval = 0x0;
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else
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rval = 0x2;
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for (i = 0 ; i < 11 ; i++) {
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clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
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rval << 24);
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clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
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rval << 24);
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clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
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rval << 24);
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clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
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rval << 24);
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}
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for (i = 0; i < 31; i++)
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clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
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/* set PLL configuration */
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if (CONFIG_DRAM_CLK >= 480)
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setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
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else
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setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
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/* Auto detect dram config, set 2 rank and 16bit bus-width */
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para->cs1 = 0;
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para->rank = 2;
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para->bus_width = 16;
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mctl_set_cr(para);
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/* Open DQS gating */
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clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
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clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
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if (para->dram_type == DRAM_TYPE_LPDDR3)
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clrsetbits_le32(&mctl_ctl->dxccr, (0x1 << 27) | (0x3<<6) ,
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0x1 << 31);
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if (readl(&mctl_com->cr) & 0x1)
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writel(0x00000303, &mctl_ctl->odtmap);
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else
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writel(0x00000201, &mctl_ctl->odtmap);
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mctl_data_train_cfg(para);
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/* ZQ calibration */
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clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
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clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
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/* CA calibration */
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if (para->dram_type == DRAM_TYPE_DDR3)
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mctl_set_pir(0x0201f3 | 0x1<<10);
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else
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mctl_set_pir(0x020173 | 0x1<<10);
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/* DQS gate training */
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if (mctl_train_dram(para) != 0) {
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low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
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high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
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if (low_data_lines_status == 0x3)
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return -EIO;
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/* DRAM has only one rank */
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para->rank = 1;
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mctl_set_cr(para);
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if (low_data_lines_status == high_data_lines_status)
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goto done; /* 16 bit bus, 1 rank */
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if (!(low_data_lines_status & high_data_lines_status)) {
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/* Retry 16 bit bus-width with CS1 set */
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para->cs1 = 1;
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mctl_set_cr(para);
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if (mctl_train_dram(para) == 0)
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goto done;
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}
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/* Try 8 bit bus-width */
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writel(0x0, DXnGCR0(1)); /* Disable high DQ */
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para->cs1 = 0;
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para->bus_width = 8;
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mctl_set_cr(para);
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if (mctl_train_dram(para) != 0)
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return -EIO;
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}
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done:
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/* Check the dramc status */
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mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
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/* Close DQS gating */
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setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
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/* set PGCR3,CKE polarity */
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writel(0x00aa0060, &mctl_ctl->pgcr3);
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/* Enable master access */
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writel(0xffffffff, &mctl_com->maer);
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return 0;
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}
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static void mctl_sys_init(struct dram_para *para)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
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clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
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clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
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clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
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clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
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udelay(1000);
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clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
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clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
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clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
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CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
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CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
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|
mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
|
|
|
|
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
|
|
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
|
|
setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
|
|
setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
|
|
|
|
para->rank = 2;
|
|
para->bus_width = 16;
|
|
mctl_set_cr(para);
|
|
|
|
/* Set dram master access priority */
|
|
writel(0x0000e00f, &mctl_ctl->clken); /* normal */
|
|
|
|
udelay(250);
|
|
}
|
|
|
|
unsigned long sunxi_dram_init(void)
|
|
{
|
|
struct sunxi_mctl_com_reg * const mctl_com =
|
|
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
|
|
struct sunxi_mctl_ctl_reg * const mctl_ctl =
|
|
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
|
|
|
|
struct dram_para para = {
|
|
.cs1 = 0,
|
|
.bank = 1,
|
|
.rank = 1,
|
|
.rows = 15,
|
|
.bus_width = 16,
|
|
.page_size = 2048,
|
|
};
|
|
|
|
#if defined(CONFIG_MACH_SUN8I_A83T)
|
|
#if (CONFIG_DRAM_TYPE == 3) || (CONFIG_DRAM_TYPE == 7)
|
|
para.dram_type = CONFIG_DRAM_TYPE;
|
|
#else
|
|
#error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3)
|
|
#endif
|
|
#endif
|
|
setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
|
|
|
|
writel(0, (SUNXI_PRCM_BASE + 0x1e8));
|
|
udelay(10);
|
|
|
|
mctl_sys_init(¶);
|
|
|
|
if (mctl_channel_init(¶) != 0)
|
|
return 0;
|
|
|
|
auto_detect_dram_size(¶);
|
|
|
|
/* Enable master software clk */
|
|
writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
|
|
|
|
/* Set DRAM ODT MAP */
|
|
if (para.rank == 2)
|
|
writel(0x00000303, &mctl_ctl->odtmap);
|
|
else
|
|
writel(0x00000201, &mctl_ctl->odtmap);
|
|
|
|
return para.page_size * (para.bus_width / 8) *
|
|
(1 << (para.bank + para.rank + para.rows));
|
|
}
|
|
|