upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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393 lines
11 KiB
393 lines
11 KiB
/*
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* Based on acpi.c from coreboot
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*
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* Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/post.h>
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#include <linux/string.h>
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#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
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#define ACPI_TABLE_CREATOR "UBOOT " /* Must be 8 bytes long! */
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#define OEM_ID "UBOOT " /* Must be 6 bytes long! */
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#define ASLC "INTL" /* Must be 4 bytes long! */
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#define OEM_REVISION 42
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#define ASL_COMPILER_REVISION 42
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/* IO ports to generate SMIs */
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#define APM_CNT 0xb2
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#define APM_CNT_CST_CONTROL 0x85
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#define APM_CNT_PST_CONTROL 0x80
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#define APM_CNT_ACPI_DISABLE 0x1e
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#define APM_CNT_ACPI_ENABLE 0xe1
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#define APM_CNT_MBI_UPDATE 0xeb
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#define APM_CNT_GNVS_UPDATE 0xea
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#define APM_CNT_FINALIZE 0xcb
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#define APM_CNT_LEGACY 0xcc
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#define APM_ST 0xb3
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/* Multiple Processor Interrupts */
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#define MP_IRQ_POLARITY_DEFAULT 0x0
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#define MP_IRQ_POLARITY_HIGH 0x1
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#define MP_IRQ_POLARITY_LOW 0x3
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#define MP_IRQ_POLARITY_MASK 0x3
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#define MP_IRQ_TRIGGER_DEFAULT 0x0
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#define MP_IRQ_TRIGGER_EDGE 0x4
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#define MP_IRQ_TRIGGER_LEVEL 0xc
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#define MP_IRQ_TRIGGER_MASK 0xc
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/*
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* Interrupt assigned for SCI in order to
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* create the ACPI MADT IRQ override entry
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*/
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#define ACTL 0x00
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#define SCIS_MASK 0x07
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#define SCIS_IRQ9 0x00
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#define SCIS_IRQ10 0x01
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#define SCIS_IRQ11 0x02
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#define SCIS_IRQ20 0x04
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#define SCIS_IRQ21 0x05
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#define SCIS_IRQ22 0x06
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#define SCIS_IRQ23 0x07
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#define ACPI_REV_ACPI_1_0 1
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#define ACPI_REV_ACPI_2_0 1
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#define ACPI_REV_ACPI_3_0 2
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#define ACPI_REV_ACPI_4_0 3
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#define ACPI_REV_ACPI_5_0 5
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#define ACPI_RSDP_REV_ACPI_1_0 0
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#define ACPI_RSDP_REV_ACPI_2_0 2
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typedef struct acpi_gen_regaddr {
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u8 space_id; /* Address space ID */
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u8 bit_width; /* Register size in bits */
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u8 bit_offset; /* Register bit offset */
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union {
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/* Reserved in ACPI 2.0 - 2.0b */
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u8 resv;
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/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
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u8 access_size;
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};
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u32 addrl; /* Register address, low 32 bits */
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u32 addrh; /* Register address, high 32 bits */
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} acpi_addr_t;
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/*
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* RSDP (Root System Description Pointer)
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* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
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*/
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struct acpi_rsdp {
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char signature[8]; /* RSDP signature */
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u8 checksum; /* Checksum of the first 20 bytes */
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char oem_id[6]; /* OEM ID */
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u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
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u32 rsdt_address; /* Physical address of RSDT (32 bits) */
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u32 length; /* Total RSDP length (incl. extended part) */
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u64 xsdt_address; /* Physical address of XSDT (64 bits) */
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u8 ext_checksum; /* Checksum of the whole table */
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u8 reserved[3];
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};
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enum acpi_address_space_type {
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ACPI_ADDRESS_SPACE_MEMORY = 0, /* System memory */
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ACPI_ADDRESS_SPACE_IO, /* System I/O */
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ACPI_ADDRESS_SPACE_PCI, /* PCI config space */
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ACPI_ADDRESS_SPACE_EC, /* Embedded controller */
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ACPI_ADDRESS_SPACE_SMBUS, /* SMBus */
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ACPI_ADDRESS_SPACE_PCC = 0x0a, /* Platform Comm. Channel */
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ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */
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};
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/* functional fixed hardware */
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#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */
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#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */
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#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */
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#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */
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#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */
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#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */
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/* Access size definitions for Generic address structure */
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enum acpi_address_space_size {
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ACPI_ACCESS_SIZE_UNDEFINED = 0, /* Undefined (legacy reasons) */
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ACPI_ACCESS_SIZE_BYTE_ACCESS = 1,
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ACPI_ACCESS_SIZE_WORD_ACCESS = 2,
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ACPI_ACCESS_SIZE_DWORD_ACCESS = 3,
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ACPI_ACCESS_SIZE_QWORD_ACCESS = 4
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};
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/* Generic ACPI header, provided by (almost) all tables */
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typedef struct acpi_table_header {
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char signature[4]; /* ACPI signature (4 ASCII characters) */
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u32 length; /* Table length in bytes (incl. header) */
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u8 revision; /* Table version (not ACPI version!) */
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volatile u8 checksum; /* To make sum of entire table == 0 */
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char oem_id[6]; /* OEM identification */
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char oem_table_id[8]; /* OEM table identification */
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u32 oem_revision; /* OEM revision number */
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char asl_compiler_id[4]; /* ASL compiler vendor ID */
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u32 asl_compiler_revision; /* ASL compiler revision number */
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} acpi_header_t;
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/* A maximum number of 32 ACPI tables ought to be enough for now */
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#define MAX_ACPI_TABLES 32
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/* RSDT (Root System Description Table) */
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struct acpi_rsdt {
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struct acpi_table_header header;
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u32 entry[MAX_ACPI_TABLES];
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};
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/* XSDT (Extended System Description Table) */
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struct acpi_xsdt {
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struct acpi_table_header header;
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u64 entry[MAX_ACPI_TABLES];
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};
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/* MCFG (PCI Express MMIO config space BAR description table) */
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struct acpi_mcfg {
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struct acpi_table_header header;
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u8 reserved[8];
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};
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struct acpi_mcfg_mmconfig {
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u32 base_address;
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u32 base_reserved;
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u16 pci_segment_group_number;
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u8 start_bus_number;
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u8 end_bus_number;
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u8 reserved[4];
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};
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/* MADT (Multiple APIC Description Table) */
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struct acpi_madt {
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struct acpi_table_header header;
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u32 lapic_addr; /* Local APIC address */
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u32 flags; /* Multiple APIC flags */
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} acpi_madt_t;
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enum dev_scope_type {
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SCOPE_PCI_ENDPOINT = 1,
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SCOPE_PCI_SUB = 2,
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SCOPE_IOAPIC = 3,
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SCOPE_MSI_HPET = 4
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};
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typedef struct dev_scope {
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u8 type;
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u8 length;
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u8 reserved[2];
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u8 enumeration;
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u8 start_bus;
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struct {
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u8 dev;
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u8 fn;
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} path[0];
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} __packed dev_scope_t;
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/* MADT: APIC Structure Type*/
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enum acpi_apic_types {
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LOCALAPIC = 0, /* Processor local APIC */
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IOAPIC, /* I/O APIC */
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IRQSOURCEOVERRIDE, /* Interrupt source override */
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NMITYPE, /* NMI source */
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LOCALNMITYPE, /* Local APIC NMI */
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LAPICADDRESSOVERRIDE, /* Local APIC address override */
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IOSAPIC, /* I/O SAPIC */
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LOCALSAPIC, /* Local SAPIC */
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PLATFORMIRQSOURCES, /* Platform interrupt sources */
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LOCALX2SAPIC, /* Processor local x2APIC */
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LOCALX2APICNMI, /* Local x2APIC NMI */
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};
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/* MADT: Processor Local APIC Structure */
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struct acpi_madt_lapic {
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u8 type; /* Type (0) */
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u8 length; /* Length in bytes (8) */
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u8 processor_id; /* ACPI processor ID */
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u8 apic_id; /* Local APIC ID */
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u32 flags; /* Local APIC flags */
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};
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#define LOCAL_APIC_FLAG_ENABLED (1 << 0)
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/* bits 1-31: reserved */
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#define PCAT_COMPAT (1 << 0)
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/* bits 1-31: reserved */
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/* MADT: Local APIC NMI Structure */
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struct acpi_madt_lapic_nmi {
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u8 type; /* Type (4) */
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u8 length; /* Length in bytes (6) */
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u8 processor_id; /* ACPI processor ID */
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u16 flags; /* MPS INTI flags */
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u8 lint; /* Local APIC LINT# */
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};
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/* MADT: I/O APIC Structure */
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struct acpi_madt_ioapic {
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u8 type; /* Type (1) */
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u8 length; /* Length in bytes (12) */
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u8 ioapic_id; /* I/O APIC ID */
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u8 reserved;
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u32 ioapic_addr; /* I/O APIC address */
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u32 gsi_base; /* Global system interrupt base */
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};
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/* MADT: Interrupt Source Override Structure */
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struct acpi_madt_irqoverride {
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u8 type; /* Type (2) */
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u8 length; /* Length in bytes (10) */
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u8 bus; /* ISA (0) */
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u8 source; /* Bus-relative int. source (IRQ) */
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u32 gsirq; /* Global system interrupt */
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u16 flags; /* MPS INTI flags */
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};
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/* FADT (Fixed ACPI Description Table) */
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struct __packed acpi_fadt {
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struct acpi_table_header header;
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u32 firmware_ctrl;
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u32 dsdt;
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u8 model;
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u8 preferred_pm_profile;
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u16 sci_int;
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u32 smi_cmd;
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u8 acpi_enable;
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u8 acpi_disable;
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u8 s4bios_req;
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u8 pstate_cnt;
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u32 pm1a_evt_blk;
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u32 pm1b_evt_blk;
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u32 pm1a_cnt_blk;
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u32 pm1b_cnt_blk;
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u32 pm2_cnt_blk;
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u32 pm_tmr_blk;
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u32 gpe0_blk;
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u32 gpe1_blk;
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u8 pm1_evt_len;
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u8 pm1_cnt_len;
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u8 pm2_cnt_len;
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u8 pm_tmr_len;
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u8 gpe0_blk_len;
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u8 gpe1_blk_len;
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u8 gpe1_base;
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u8 cst_cnt;
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u16 p_lvl2_lat;
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u16 p_lvl3_lat;
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u16 flush_size;
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u16 flush_stride;
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u8 duty_offset;
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u8 duty_width;
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u8 day_alrm;
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u8 mon_alrm;
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u8 century;
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u16 iapc_boot_arch;
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u8 res2;
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u32 flags;
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struct acpi_gen_regaddr reset_reg;
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u8 reset_value;
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u8 res3;
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u8 res4;
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u8 res5;
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u32 x_firmware_ctl_l;
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u32 x_firmware_ctl_h;
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u32 x_dsdt_l;
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u32 x_dsdt_h;
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struct acpi_gen_regaddr x_pm1a_evt_blk;
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struct acpi_gen_regaddr x_pm1b_evt_blk;
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struct acpi_gen_regaddr x_pm1a_cnt_blk;
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struct acpi_gen_regaddr x_pm1b_cnt_blk;
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struct acpi_gen_regaddr x_pm2_cnt_blk;
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struct acpi_gen_regaddr x_pm_tmr_blk;
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struct acpi_gen_regaddr x_gpe0_blk;
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struct acpi_gen_regaddr x_gpe1_blk;
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};
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/* Flags for p_lvl2_lat and p_lvl3_lat */
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#define ACPI_FADT_C2_NOT_SUPPORTED 101
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#define ACPI_FADT_C3_NOT_SUPPORTED 1001
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/* FADT Feature Flags */
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#define ACPI_FADT_WBINVD (1 << 0)
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#define ACPI_FADT_WBINVD_FLUSH (1 << 1)
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#define ACPI_FADT_C1_SUPPORTED (1 << 2)
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#define ACPI_FADT_C2_MP_SUPPORTED (1 << 3)
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#define ACPI_FADT_POWER_BUTTON (1 << 4)
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#define ACPI_FADT_SLEEP_BUTTON (1 << 5)
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#define ACPI_FADT_FIXED_RTC (1 << 6)
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#define ACPI_FADT_S4_RTC_WAKE (1 << 7)
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#define ACPI_FADT_32BIT_TIMER (1 << 8)
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#define ACPI_FADT_DOCKING_SUPPORTED (1 << 9)
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#define ACPI_FADT_RESET_REGISTER (1 << 10)
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#define ACPI_FADT_SEALED_CASE (1 << 11)
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#define ACPI_FADT_HEADLESS (1 << 12)
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#define ACPI_FADT_SLEEP_TYPE (1 << 13)
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#define ACPI_FADT_PCI_EXPRESS_WAKE (1 << 14)
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#define ACPI_FADT_PLATFORM_CLOCK (1 << 15)
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#define ACPI_FADT_S4_RTC_VALID (1 << 16)
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#define ACPI_FADT_REMOTE_POWER_ON (1 << 17)
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#define ACPI_FADT_APIC_CLUSTER (1 << 18)
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#define ACPI_FADT_APIC_PHYSICAL (1 << 19)
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/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
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#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
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#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
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/* bits 22-31: reserved ACPI 5.0 */
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/* FADT Boot Architecture Flags */
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#define ACPI_FADT_LEGACY_DEVICES (1 << 0)
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#define ACPI_FADT_8042 (1 << 1)
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#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
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#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
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#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
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/* No legacy devices (including 8042) */
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#define ACPI_FADT_LEGACY_FREE 0x00
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/* FADT Preferred Power Management Profile */
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#define PM_UNSPECIFIED 0
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#define PM_DESKTOP 1
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#define PM_MOBILE 2
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#define PM_WORKSTATION 3
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#define PM_ENTERPRISE_SERVER 4
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#define PM_SOHO_SERVER 5
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#define PM_APPLIANCE_PC 6
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#define PM_PERFORMANCE_SERVER 7
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#define PM_TABLET 8 /* ACPI 5.0 */
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/* FACS (Firmware ACPI Control Structure) */
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struct acpi_facs {
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char signature[4]; /* "FACS" */
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u32 length; /* Length in bytes (>= 64) */
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u32 hardware_signature; /* Hardware signature */
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u32 firmware_waking_vector; /* Firmware waking vector */
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u32 global_lock; /* Global lock */
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u32 flags; /* FACS flags */
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u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
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u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
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u8 version; /* ACPI 4.0: 2 */
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u8 resv[31]; /* FIXME: 4.0: ospm_flags */
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};
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/* FACS flags */
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#define ACPI_FACS_S4BIOS_F (1 << 0)
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#define ACPI_FACS_64BIT_WAKE_F (1 << 1)
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/* Bits 31..2: reserved */
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/* These can be used by the target port */
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unsigned long acpi_create_madt_lapics(unsigned long current);
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int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
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u32 gsi_base);
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int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
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u8 bus, u8 source, u32 gsirq, u16 flags);
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unsigned long acpi_fill_madt(unsigned long current);
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void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
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void *dsdt);
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int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
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u16 flags, u8 lint);
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unsigned long write_acpi_tables(unsigned long start);
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