upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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257 lines
6.1 KiB
257 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#ifdef CONFIG_FSL_LS_PPA
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#include <asm/arch/ppa.h>
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#endif
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#include <asm/arch/fdt.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/soc.h>
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#include <ahci.h>
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#include <hwconfig.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_esdhc.h>
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#include <fsl_mmdc.h>
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#include <spl.h>
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#include <netdev.h>
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#include "../common/qixis.h"
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#include "ls1012aqds_qixis.h"
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#include "ls1012aqds_pfe.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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sw = QIXIS_READ(arch);
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printf("Board Arch: V%d, ", sw >> 4);
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
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sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
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if (sw & QIXIS_LBMAP_ALTBANK)
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printf("flash: 2\n");
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else
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printf("flash: 1\n");
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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return 0;
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}
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int dram_init(void)
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{
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static const struct fsl_mmdc_info mparam = {
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0x05180000, /* mdctl */
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0x00030035, /* mdpdc */
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0x12554000, /* mdotc */
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0xbabf7954, /* mdcfg0 */
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0xdb328f64, /* mdcfg1 */
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0x01ff00db, /* mdcfg2 */
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0x00001680, /* mdmisc */
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0x0f3c8000, /* mdref */
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0x00002000, /* mdrwd */
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0x00bf1023, /* mdor */
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0x0000003f, /* mdasp */
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0x0000022a, /* mpodtctrl */
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0xa1390003, /* mpzqhwctrl */
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};
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mmdc_init(&mparam);
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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#endif
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return 0;
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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u8 mux_sdhc_cd = 0x80;
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i2c_set_bus_num(0);
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i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
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return 0;
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}
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#endif
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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/* Set CCI-400 control override register to enable barrier
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* transaction */
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out_le32(&cci->ctrl_ord,
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CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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erratum_a010315();
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#endif
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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return 0;
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}
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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char esdhc0_path[] = "/soc/esdhc@1560000";
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char esdhc1_path[] = "/soc/esdhc@1580000";
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u8 card_id;
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do_fixup_by_path(blob, esdhc0_path, "status", "okay",
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sizeof("okay"), 1);
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/*
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* The Presence Detect 2 register detects the installation
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* of cards in various PCI Express or SGMII slots.
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*
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* STAT_PRS2[7:5]: Specifies the type of card installed in the
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* SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
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*/
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card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
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/* If no adapter is installed in SDHC2, disable SDHC2 */
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if (card_id == 0x7)
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do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
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sizeof("disabled"), 1);
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else
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do_fixup_by_path(blob, esdhc1_path, "status", "okay",
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sizeof("okay"), 1);
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return 0;
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}
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static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
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char *enet_path, char *mdio_path)
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{
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do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
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&prop_val.busid, PFE_PROP_LEN, 1);
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do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
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&prop_val.phyid, PFE_PROP_LEN, 1);
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do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
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&prop_val.mux_val, PFE_PROP_LEN, 1);
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do_fixup_by_path(set_blob, enet_path, "phy-mode",
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prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
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do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
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&prop_val.phy_mask, PFE_PROP_LEN, 1);
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return 0;
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}
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static void fdt_fsl_fixup_of_pfe(void *blob)
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{
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int i = 0;
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struct pfe_prop_val prop_val;
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void *l_blob = blob;
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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for (i = 0; i < NUM_ETH_NODE; i++) {
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switch (srds_s1) {
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case SERDES_1_G_PROTOCOL:
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if (i == 0) {
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prop_val.busid = cpu_to_fdt32(
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ETH_1_1G_BUS_ID);
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prop_val.phyid = cpu_to_fdt32(
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ETH_1_1G_PHY_ID);
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prop_val.mux_val = cpu_to_fdt32(
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ETH_1_1G_MDIO_MUX);
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prop_val.phy_mask = cpu_to_fdt32(
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ETH_1G_MDIO_PHY_MASK);
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prop_val.phy_mode = "sgmii";
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pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
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ETH_1_MDIO);
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} else {
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prop_val.busid = cpu_to_fdt32(
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ETH_2_1G_BUS_ID);
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prop_val.phyid = cpu_to_fdt32(
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ETH_2_1G_PHY_ID);
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prop_val.mux_val = cpu_to_fdt32(
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ETH_2_1G_MDIO_MUX);
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prop_val.phy_mask = cpu_to_fdt32(
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ETH_1G_MDIO_PHY_MASK);
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prop_val.phy_mode = "rgmii";
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pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
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ETH_2_MDIO);
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}
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break;
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case SERDES_2_5_G_PROTOCOL:
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if (i == 0) {
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prop_val.busid = cpu_to_fdt32(
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ETH_1_2_5G_BUS_ID);
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prop_val.phyid = cpu_to_fdt32(
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ETH_1_2_5G_PHY_ID);
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prop_val.mux_val = cpu_to_fdt32(
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ETH_1_2_5G_MDIO_MUX);
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prop_val.phy_mask = cpu_to_fdt32(
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ETH_2_5G_MDIO_PHY_MASK);
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prop_val.phy_mode = "sgmii-2500";
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pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
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ETH_1_MDIO);
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} else {
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prop_val.busid = cpu_to_fdt32(
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ETH_2_2_5G_BUS_ID);
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prop_val.phyid = cpu_to_fdt32(
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ETH_2_2_5G_PHY_ID);
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prop_val.mux_val = cpu_to_fdt32(
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ETH_2_2_5G_MDIO_MUX);
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prop_val.phy_mask = cpu_to_fdt32(
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ETH_2_5G_MDIO_PHY_MASK);
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prop_val.phy_mode = "sgmii-2500";
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pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
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ETH_2_MDIO);
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}
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break;
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default:
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printf("serdes:[%d]\n", srds_s1);
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}
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}
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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fdt_fsl_fixup_of_pfe(blob);
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return 0;
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}
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#endif
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