upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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108 lines
2.5 KiB
108 lines
2.5 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C Copyright 2009
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* Stefano Babic DENX Software Engineering sbabic@denx.de.
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM spi
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Setting IOMUXC */
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DATA 4 0x73FA88a0 0x200
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DATA 4 0x73FA850c 0x20c5
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DATA 4 0x73FA8510 0x20c5
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DATA 4 0x73FA883c 0x2
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DATA 4 0x73FA8848 0x2
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DATA 4 0x73FA84b8 0xe7
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DATA 4 0x73FA84bc 0x45
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DATA 4 0x73FA84c0 0x45
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DATA 4 0x73FA84c4 0x45
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DATA 4 0x73FA84c8 0x45
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DATA 4 0x73FA8820 0x0
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DATA 4 0x73FA84a4 0x3
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DATA 4 0x73FA84a8 0x3
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DATA 4 0x73FA84ac 0xe3
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DATA 4 0x73FA84b0 0xe3
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DATA 4 0x73FA84b4 0xe3
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DATA 4 0x73FA84cc 0xe3
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DATA 4 0x73FA84d0 0xe2
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DATA 4 0x73FA882c 0x6
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DATA 4 0x73FA88a4 0x6
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DATA 4 0x73FA88ac 0x6
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DATA 4 0x73FA88b8 0x6
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/*
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* Setting DDR for micron
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* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
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* CAS=3 BL=4
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*/
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/* ESDCTL_ESDCTL0 */
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DATA 4 0x83FD9000 0x82a20000
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/* ESDCTL_ESDCTL1 */
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DATA 4 0x83FD9008 0x82a20000
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/* ESDCTL_ESDMISC */
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DATA 4 0x83FD9010 0x000ad0d0
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/* ESDCTL_ESDCFG0 */
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DATA 4 0x83FD9004 0x333574aa
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/* ESDCTL_ESDCFG1 */
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DATA 4 0x83FD900C 0x333574aa
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/* Init DRAM on CS0 */
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/* ESDCTL_ESDSCR */
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DATA 4 0x83FD9014 0x04008008
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DATA 4 0x83FD9014 0x0000801a
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DATA 4 0x83FD9014 0x0000801b
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DATA 4 0x83FD9014 0x00448019
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DATA 4 0x83FD9014 0x07328018
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DATA 4 0x83FD9014 0x04008008
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DATA 4 0x83FD9014 0x00008010
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DATA 4 0x83FD9014 0x00008010
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DATA 4 0x83FD9014 0x06328018
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DATA 4 0x83FD9014 0x03808019
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DATA 4 0x83FD9014 0x00408019
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DATA 4 0x83FD9014 0x00008000
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/* Init DRAM on CS1 */
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DATA 4 0x83FD9014 0x0400800c
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DATA 4 0x83FD9014 0x0000801e
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DATA 4 0x83FD9014 0x0000801f
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DATA 4 0x83FD9014 0x0000801d
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DATA 4 0x83FD9014 0x0732801c
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DATA 4 0x83FD9014 0x0400800c
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DATA 4 0x83FD9014 0x00008014
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DATA 4 0x83FD9014 0x00008014
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DATA 4 0x83FD9014 0x0632801c
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DATA 4 0x83FD9014 0x0380801d
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DATA 4 0x83FD9014 0x0040801d
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DATA 4 0x83FD9014 0x00008004
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/* Write to CTL0 */
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DATA 4 0x83FD9000 0xb2a20000
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/* Write to CTL1 */
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DATA 4 0x83FD9008 0xb2a20000
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/* ESDMISC */
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DATA 4 0x83FD9010 0x000ad6d0
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/* ESDCTL_ESDCDLYGD */
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DATA 4 0x83FD9034 0x90000000
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DATA 4 0x83FD9014 0x00000000
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