upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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227 lines
4.8 KiB
227 lines
4.8 KiB
if TARGET_MX6MEMCAL
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config SYS_BOARD
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default "mx6memcal"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "mx6memcal"
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menu "mx6memcal specifics"
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choice
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prompt "Serial console"
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help
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Either UART1 or UART2 will be used as the console for
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displaying the calibration values or errors.
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config SERIAL_CONSOLE_UART1
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bool "UART1"
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help
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Select this if your board uses UART1 for its' console.
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config SERIAL_CONSOLE_UART2
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bool "UART2"
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help
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Select this if your board uses UART2 for its' console.
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endchoice
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choice
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prompt "UART pads"
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help
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Select the RX and TX pads used for your serial console.
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The choices below reflect the most commonly used options
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for your UART.
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config UART2_EIM_D26_27
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bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)"
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depends on SERIAL_CONSOLE_UART2
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help
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Choose this configuration if you're using pads
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EIM_D26 and D27 for a console on UART2.
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This is typical for designs that are based on the
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NXP SABRELite.
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config UART1_CSI0_DAT10_11
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bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)"
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depends on SERIAL_CONSOLE_UART1
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help
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Choose this configuration if you're using pads
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CSI0_DAT10 and DAT11 for a console on UART1 as
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is done on the i.MX6 Wand board and i.MX6 SabreSD.
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config UART1_UART1
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bool "UART1 on UART1 (i.MX6SL EVK, WaRP)"
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depends on SERIAL_CONSOLE_UART1
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help
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Choose this configuration if you're using pads
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UART1_TXD/RXD for a console on UART1 as is done
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on most i.MX6SL designs.
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endchoice
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config IMXIMAGE_OUTPUT
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bool "Include output for imximage .cfg files"
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default y
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help
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Say "Y" if you want output formatted for use in non-SPL
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(DCD-style) configuration files.
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config DDRWIDTH
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int "DDR bus width"
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default 64
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help
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Select either 32 or 64 to reflect the DDR bus width.
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config DDRCS
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int "DDR chip selects"
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default 2
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range 1 2
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help
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Select the number of chip selects used in your board design
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choice
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prompt "Memory type"
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help
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Select the type of DDR (DDR3 or LPDDR2) used on your design
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config DDR3
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bool "DDR3"
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help
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Select this if your board design uses DDR3.
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config LPDDR2
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bool "LPDDR2"
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help
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Select this if your board design uses LPDDR2.
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endchoice
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choice
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prompt "Memory device"
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config MT41K512M16TNA
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bool "Micron MT41K512M16TNA 512Mx16 (1GiB/chip)"
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depends on DDR3
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config MT41K128M16JT
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bool "Micron MT41K128M16JT 128Mx16 (256 MiB/chip)"
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depends on DDR3
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config H5TQ4G63AFR
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bool "Hynix H5TQ4G63AFR 256Mx16 (512 MiB/chip)"
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depends on DDR3
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config H5TQ2G63DFR
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bool "Hynix H5TQ2G63DFR 128Mx16 (256 MiB/chip)"
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depends on DDR3
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config MT42L256M32D2LG
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bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
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depends on LPDDR2
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config MT29PZZZ4D4BKESK
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bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
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depends on LPDDR2
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endchoice
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config DDR_ODT
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int "DDR On-die-termination"
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default 2
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range 0 7
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help
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Enter the on-die termination value as an index defined for
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IOMUX settings for PAD_DRAM_SDCLK0_P and others.
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0 == Disabled
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1 == 120 Ohm
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2 == 60 Ohm
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3 == 40 Ohm
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4 == 30 Ohm
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5 == 24 Ohm
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6 == 20 Ohm
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7 == 17 Ohm
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Value will be applied to all clock and data lines
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config DRAM_DRIVE_STRENGTH
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int "DRAM Drive strength"
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default 6
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range 0 7
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help
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Enter drive strength as an index defined for IOMUX settings
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for GRP_B1DS and others.
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0 == Hi Z
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6 == 40 Ohm (default)
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7 == 34 Ohm
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Value will be applied to all clock and data lines
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config RTT_NOM
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int "RTT_NOM"
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default 1
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range 1 2
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help
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Enter the RTT_NOM selector
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1 == RZQ/4 (60ohm)
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2 == RZQ/2 (120ohm)
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config RTT_WR
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int "RTT_WR"
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default 1
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range 0 2
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help
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Enter the RTT_WR selector for MR2
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0 == Dynamic ODT disabled
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1 == RZQ/4 (60ohm)
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2 == RZQ/2 (120ohm)
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config RALAT
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int "Read additional latency"
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default 5
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range 0 7
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help
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Enter a latency in number of cycles. This will be added to
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CAS and internal delays for which the MMDC will retrieve the
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read data from the internal FIFO.
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This is used to compensate for board/chip delays.
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config WALAT
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int "Write additional latency"
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default 0
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range 0 7
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help
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Enter a latency in number of cycles. This will be added to
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CAS and internal delays for which the MMDC will retrieve the
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read data from the internal FIFO
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This is used to compensate for board/chip delays.
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config REFSEL
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int "Refresh period"
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range 0 3
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default 1
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help
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Select the DDR refresh period.
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See the description of bitfield REF_SEL in the reference manual
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for details.
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0 == disabled
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1 == 32 kHz
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2 == 64 kHz
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3 == fast counter
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config REFR
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int "Number of refreshes"
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range 0 7
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default 7
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help
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This selects the number of refreshes (-1) during each period.
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i.e.:
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0 == 1 refresh (tRFC)
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7 == 8 refreshes (tRFC*8)
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See the description of MDREF[REFR] in the reference manual for
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details.
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endmenu
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endif
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