upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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299 lines
8.5 KiB
299 lines
8.5 KiB
/*
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* (C) Copyright 2002
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* Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <ata.h>
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#include "memio.h"
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#include "articiaS.h"
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#include "via686.h"
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#include "i8259.h"
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DECLARE_GLOBAL_DATA_PTR;
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#undef VIA_DEBUG
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#ifdef VIA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/* Setup the ISA-to-PCI host bridge */
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void via_isa_init(pci_dev_t dev, struct pci_config_table *table)
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{
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char regval;
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if (PCI_FUNC(dev) == 0)
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{
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PRINTF("... PCI-to-ISA bridge, dev=0x%X\n", dev);
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/* Enable I/O Recovery time */
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pci_write_config_byte(dev, 0x40, 0x08);
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/* Enable ISA refresh */
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pci_write_config_byte(dev, 0x41, 0x41); /* was 01 */
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/* Enable ISA line buffer */
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pci_write_config_byte(dev, 0x45, 0x80);
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/* Gate INTR, and flush line buffer */
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pci_write_config_byte(dev, 0x46, 0x60);
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/* Enable EISA ports 4D0/4D1. Do we need this ? */
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pci_write_config_byte(dev, 0x47, 0xe6); /* was 20 */
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/* 512 K PCI Decode */
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pci_write_config_byte(dev, 0x48, 0x01);
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/* Wait for PGNT before grant to ISA Master/DMA */
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/* ports 0-FF to SDBus */
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/* IRQ 14 and 15 for ide 0/1 */
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pci_write_config_byte(dev, 0x4a, 0x04); /* Was c4 */
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/* Plug'n'Play */
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/* Parallel DRQ 3, Floppy DRQ 2 (default) */
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pci_write_config_byte(dev, 0x50, 0x0e);
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/* IRQ Routing for Floppy and Parallel port */
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/* IRQ 6 for floppy, IRQ 7 for parallel port */
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pci_write_config_byte(dev, 0x51, 0x76);
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/* IRQ Routing for serial ports (take IRQ 3 and 4) */
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pci_write_config_byte(dev, 0x52, 0x34);
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/* All IRQ's level triggered. */
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pci_write_config_byte(dev, 0x54, 0x00);
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/* PCI IRQ's all at IRQ 9 */
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pci_write_config_byte(dev, 0x55, 0x90);
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pci_write_config_byte(dev, 0x56, 0x99);
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pci_write_config_byte(dev, 0x57, 0x90);
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/* Enable Keyboard */
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pci_read_config_byte(dev, 0x5A, ®val);
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regval |= 0x01;
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pci_write_config_byte(dev, 0x5A, regval);
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pci_write_config_byte(dev, 0x80, 0);
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pci_write_config_byte(dev, 0x85, 0x01);
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/* pci_write_config_byte(dev, 0x77, 0x00); */
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}
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}
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/*
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* Initialize PNP irq routing
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*/
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void via_init_irq_routing(uint8 irq_map[])
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{
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char *s;
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uint8 level_edge_bits = 0xf;
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/* Set irq routings */
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pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4);
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pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4);
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pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4);
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/*
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* Gather level/edge bits
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* Default is to assume level triggered
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*/
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s = getenv("pci_irqa_select");
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if (s && strcmp(s, "level") == 0)
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level_edge_bits &= ~0x01;
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s = getenv("pci_irqb_select");
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if (s && strcmp(s, "level") == 0)
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level_edge_bits &= ~0x02;
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s = getenv("pci_irqc_select");
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if (s && strcmp(s, "level") == 0)
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level_edge_bits &= ~0x04;
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s = getenv("pci_irqd_select");
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if (s && strcmp(s, "level") == 0)
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level_edge_bits &= ~0x08;
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PRINTF("IRQ map\n");
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PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level");
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PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level");
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PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level");
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PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level");
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pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits);
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PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54),
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pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56),
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pci_read_cfg_byte(0, 7<<3, 0x57));
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}
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/* Setup the IDE controller. This doesn't seem to work yet. I/O to an IDE controller port */
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/* always return the last character output on the serial port (!) */
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/* This function is called by the pnp-library when it encounters 0:7:1 */
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void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
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{
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PRINTF("... IDE controller, dev=0x%X\n", dev);
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/* Enable both IDE channels. */
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pci_write_config_byte(dev, 0x40, 0x03);
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/* udelay(10000); */
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/* udelay(10000); */
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/* Enable IO Space */
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pci_write_config_word(dev, 0x04, 0x03);
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/* Set to compatibility mode */
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pci_write_config_byte(dev, 0x09, 0x8A); /* WAS: 0x8f); */
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/* Set to legacy interrupt mode */
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pci_write_config_byte(dev, 0x3d, 0x00); /* WAS: 0x01); */
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}
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/* Set the base address of the floppy controller to 0x3F0 */
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void via_fdc_init(pci_dev_t dev)
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{
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unsigned char c;
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/* Enable Configuration mode */
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pci_read_config_byte(dev, 0x85, &c);
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c |= 0x02;
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pci_write_config_byte(dev, 0x85, c);
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/* Set floppy controller port to 0x3F0. */
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SIO_WRITE_CONFIG(0xE3, (0x3F<<2));
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/* Enable floppy controller */
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SIO_READ_CONFIG(0xE2, c);
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c |= 0x10;
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SIO_WRITE_CONFIG(0xE2, c);
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/* Switch of configuration mode */
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pci_read_config_byte(dev, 0x85, &c);
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c &= ~0x02;
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pci_write_config_byte(dev, 0x85, c);
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}
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/* Init function 0 of the via southbridge. Called by the pnp-library */
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void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
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{
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if (PCI_FUNC(dev) == 0)
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{
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/* FIXME: Try to generate a PCI reset */
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/* unsigned char c; */
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/* pci_read_config_byte(dev, 0x47, &c); */
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/* pci_write_config_byte(dev, 0x47, c | 0x01); */
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via_isa_init(dev, table);
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via_fdc_init(dev);
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}
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}
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__asm (" .globl via_calibrate_time_base \n"
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"via_calibrate_time_base: \n"
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" lis 9, 0xfe00 \n"
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" li 0, 0x00 \n"
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" mttbu 0 \n"
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" mttbl 0 \n"
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"ctb_loop: \n"
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" lbz 0, 0x61(9) \n"
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" eieio \n"
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" andi. 0, 0, 0x20 \n"
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" beq ctb_loop \n"
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"ctb_done: \n"
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" mftb 3 \n"
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" blr");
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extern unsigned long via_calibrate_time_base(void);
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void via_calibrate_bus_freq (void)
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{
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unsigned long tb;
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/* This is 20 microseconds */
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#define CALIBRATE_TIME 28636
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/* Enable the timer (and disable speaker) */
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unsigned char c;
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c = in_byte (0x61);
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out_byte (0x61, ((c & ~0x02) | 0x01));
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/* Set timer 2 to low/high writing */
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out_byte (0x43, 0xb0);
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out_byte (0x42, CALIBRATE_TIME & 0xff);
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out_byte (0x42, CALIBRATE_TIME >> 8);
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/* Read the time base */
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tb = via_calibrate_time_base ();
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if (tb >= 700000)
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gd->bus_clk = 133333333;
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else
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gd->bus_clk = 100000000;
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}
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void ide_led(uchar led, uchar status)
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{
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/* unsigned char c = in_byte(0x92); */
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/* if (!status) */
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/* out_byte(0x92, c | 0xC0); */
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/* else */
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/* out_byte(0x92, c & ~0xC0); */
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}
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void via_init_afterscan(void)
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{
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/* Modify IDE controller setup */
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pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20);
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pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
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pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff);
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pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b); /* FIXME: Might depend on drives connected */
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pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42); /* FIXME: Might depend on drives connected */
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pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05);
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pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18);
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pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10);
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pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22); /* FIXME: Not documented, but set in PC bios */
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pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20); /* FIXME: Not documented */
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/* Modify some values in the USB controller */
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pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17);
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pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01);
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pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12);
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pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03);
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pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40);
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pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17);
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pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01);
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pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12);
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pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03);
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pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40);
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}
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