upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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261 lines
7.2 KiB
261 lines
7.2 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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static void at91sam9260ek_serial_hw_init(void)
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{
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#ifdef CONFIG_USART0
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at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
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#endif
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#ifdef CONFIG_USART1
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at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
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at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
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#endif
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#ifdef CONFIG_USART2
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at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
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at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
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#endif
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#ifdef CONFIG_USART3 /* DBGU */
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at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
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at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
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#endif
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}
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#ifdef CONFIG_CMD_NAND
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static void at91sam9260ek_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CFG_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CFG_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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/* Configure RDY/BSY */
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at91_set_gpio_input(AT91_PIN_PC13, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(AT91_PIN_PC14, 1);
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}
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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static void at91sam9260ek_spi_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
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at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
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at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
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at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
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at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
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}
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#endif
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#ifdef CONFIG_MACB
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static void at91sam9260ek_macb_hw_init(void)
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{
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PA17) => PHY normal mode (not Test mode)
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* ERX0 (PA14) => PHY ADDR0
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* ERX1 (PA15) => PHY ADDR1
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* ERX2 (PA25) => PHY ADDR2
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* ERX3 (PA26) => PHY ADDR3
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* ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0D << 8)) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0 << 8)) |
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AT91_RSTC_URSTEN);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA17) |
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
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at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
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at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
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at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
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at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
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at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
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at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
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at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
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at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
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at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
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#ifndef CONFIG_RMII
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at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
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at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
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at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
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at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
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at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
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#if defined(CONFIG_AT91SAM9260EK)
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/*
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* use PA10, PA11 for ETX2, ETX3.
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* PA23 and PA24 are for TWI EEPROM
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*/
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at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
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at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
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#else
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at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
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at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
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#endif
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at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
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#endif
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}
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91SAM9260EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91sam9260ek_serial_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91sam9260ek_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91sam9260ek_spi_hw_init();
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#endif
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#ifdef CONFIG_MACB
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at91sam9260ek_macb_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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