upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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53 lines
1.7 KiB
53 lines
1.7 KiB
/*
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* (C) Copyright 2003
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* Ingo Assmus <ingo.assmus@keymile.com>
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* for cpci750 Reinhard Arlt
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* main board support/init for the cpci750.
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*/
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#ifndef __64360_H__
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#define __64360_H__
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/* CPU Configuration bits */
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#define CPU_CONF_ADDR_MISS_EN (1 << 8)
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#define CPU_CONF_SINGLE_CPU (1 << 11)
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#define CPU_CONF_ENDIANESS (1 << 12)
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#define CPU_CONF_PIPELINE (1 << 13)
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#define CPU_CONF_STOP_RETRY (1 << 17)
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#define CPU_CONF_MULTI_DECODE (1 << 18)
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#define CPU_CONF_DP_VALID (1 << 19)
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#define CPU_CONF_PERR_PROP (1 << 22)
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#define CPU_CONF_AACK_DELAY_2 (1 << 25)
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#define CPU_CONF_AP_VALID (1 << 26)
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#define CPU_CONF_REMAP_WR_DIS (1 << 27)
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/* CPU Master Control bits */
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#define CPU_MAST_CTL_ARB_EN (1 << 8)
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#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
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#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
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#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
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#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
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#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
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#endif /* __64360_H__ */
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