upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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75 lines
2.2 KiB
75 lines
2.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/include/asm/arch-rmobile/r8a7791.h
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*
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* Copyright (C) 2013,2014 Renesas Electronics Corporation
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*/
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#ifndef __ASM_ARCH_R8A7791_H
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#define __ASM_ARCH_R8A7791_H
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#include "rcar-base.h"
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/*
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* R-Car (R8A7791) I/O Addresses
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*/
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/* SH-I2C */
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#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
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/* SDHI */
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#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
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#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
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#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
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#define DBSC3_1_QOS_R0_BASE 0xE67A1000
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#define DBSC3_1_QOS_R1_BASE 0xE67A1100
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#define DBSC3_1_QOS_R2_BASE 0xE67A1200
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#define DBSC3_1_QOS_R3_BASE 0xE67A1300
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#define DBSC3_1_QOS_R4_BASE 0xE67A1400
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#define DBSC3_1_QOS_R5_BASE 0xE67A1500
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#define DBSC3_1_QOS_R6_BASE 0xE67A1600
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#define DBSC3_1_QOS_R7_BASE 0xE67A1700
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#define DBSC3_1_QOS_R8_BASE 0xE67A1800
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#define DBSC3_1_QOS_R9_BASE 0xE67A1900
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#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
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#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
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#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
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#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
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#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
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#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
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#define DBSC3_1_QOS_W0_BASE 0xE67A2000
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#define DBSC3_1_QOS_W1_BASE 0xE67A2100
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#define DBSC3_1_QOS_W2_BASE 0xE67A2200
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#define DBSC3_1_QOS_W3_BASE 0xE67A2300
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#define DBSC3_1_QOS_W4_BASE 0xE67A2400
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#define DBSC3_1_QOS_W5_BASE 0xE67A2500
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#define DBSC3_1_QOS_W6_BASE 0xE67A2600
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#define DBSC3_1_QOS_W7_BASE 0xE67A2700
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#define DBSC3_1_QOS_W8_BASE 0xE67A2800
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#define DBSC3_1_QOS_W9_BASE 0xE67A2900
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#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
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#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
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#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
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#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
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#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
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#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
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#define DBSC3_1_DBADJ2 0xE67A00C8
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/* Module stop control/status register bits */
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#define MSTP0_BITS 0x00640801
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#define MSTP1_BITS 0x9B6C9B5A
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#define MSTP2_BITS 0x100D21FC
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#define MSTP3_BITS 0xF08CD810
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#define MSTP4_BITS 0x800001C4
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#define MSTP5_BITS 0x44C00046
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#define MSTP7_BITS 0x05BFE618
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#define MSTP8_BITS 0x40C0FE85
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#define MSTP9_BITS 0xFF979FFF
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#define MSTP10_BITS 0xFFFEFFE0
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#define MSTP11_BITS 0x000001C0
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#define R8A7791_CUT_ES2X 2
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#define IS_R8A7791_ES2() \
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(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
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#endif /* __ASM_ARCH_R8A7791_H */
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