upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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74 lines
1.6 KiB
74 lines
1.6 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*/
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#include <clk.h>
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#include <dm/device.h>
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#include "clk-lib.h"
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#define HZ_IN_MHZ 1000000
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#define ceil(x, y) ({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; })
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int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl)
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{
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int ret;
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ulong mhz_rate, priv_rate;
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struct clk clk;
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/* Dummy fmeas device, just to be able to use standard clk_* api */
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struct udevice fmeas = {
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.name = "clk-fmeas",
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.node = ofnode_path("/clk-fmeas"),
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};
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ret = clk_get_by_name(&fmeas, name, &clk);
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if (ret) {
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pr_err("clock '%s' not found, err=%d\n", name, ret);
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return ret;
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}
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if (ctl & CLK_ON) {
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ret = clk_enable(&clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
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return ret;
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}
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if ((ctl & CLK_SET) && rate) {
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priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate;
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ret = clk_set_rate(&clk, priv_rate);
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if (ret)
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return ret;
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}
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if (ctl & CLK_OFF) {
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ret = clk_disable(&clk);
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if (ret) {
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pr_err("clock '%s' can't be disabled, err=%d\n", name, ret);
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return ret;
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}
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}
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priv_rate = clk_get_rate(&clk);
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clk_free(&clk);
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mhz_rate = ceil(priv_rate, HZ_IN_MHZ);
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if (ctl & CLK_MHZ)
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priv_rate = mhz_rate;
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if ((ctl & CLK_GET) && rate)
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*rate = priv_rate;
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if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ))
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printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate);
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else if (ctl & CLK_PRINT)
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printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate);
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else
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debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate);
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return 0;
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}
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