upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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116 lines
4.1 KiB
116 lines
4.1 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Pinmux configuration for Compulab CM-T335 board
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*
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* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
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*
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* Author: Ilya Ledvich <ilya@compulab.co.il>
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux uart1_pin_mux[] = {
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{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
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{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
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{OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
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{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
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{-1},
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};
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static struct module_pin_mux i2c0_pin_mux[] = {
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux i2c1_pin_mux[] = {
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/* I2C_DATA */
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{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
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/* I2C_SCLK */
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{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux rgmii1_pin_mux[] = {
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{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
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{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
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{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
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{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
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{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
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{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
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{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
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{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
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{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
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{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
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{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
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{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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static struct module_pin_mux eth_phy_rst_pin_mux[] = {
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{OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */
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{-1},
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};
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static struct module_pin_mux status_led_pin_mux[] = {
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{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */
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{-1},
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};
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void set_uart_mux_conf(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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configure_module_pin_mux(uart1_pin_mux);
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}
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void set_mux_conf_regs(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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configure_module_pin_mux(i2c1_pin_mux);
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configure_module_pin_mux(rgmii1_pin_mux);
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configure_module_pin_mux(eth_phy_rst_pin_mux);
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configure_module_pin_mux(mmc0_pin_mux);
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configure_module_pin_mux(nand_pin_mux);
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configure_module_pin_mux(status_led_pin_mux);
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}
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