upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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309 lines
8.2 KiB
309 lines
8.2 KiB
/*
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* (C) Copyright 2006 Detlev Zundel, dzu@denx.de
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <config.h>
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#include <mpc8xx.h>
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/*
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* Memory Controller Using
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*
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* CS0 - Flash memory (0x40000000)
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* CS3 - SDRAM (0x00000000}
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*/
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/* ------------------------------------------------------------------------- */
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#define _not_used_ 0xffffffff
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const uint sdram_table[] = {
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/* single read. (offset 0 in upm RAM) */
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0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
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0x1ff77c47,
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/* MRS initialization (offset 5) */
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0x1ff77c34, 0xefeabc34, 0x1fb57c35,
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/* burst read. (offset 8 in upm RAM) */
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0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* single write. (offset 18 in upm RAM) */
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0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* burst write. (offset 20 in upm RAM) */
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0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* refresh. (offset 30 in upm RAM) */
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0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* exception. (offset 3c in upm RAM) */
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0x7ffffc07, _not_used_, _not_used_, _not_used_
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};
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const uint nand_flash_table[] = {
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/* single read. (offset 0 in upm RAM) */
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0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
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0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
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/* burst read. (offset 8 in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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/* single write. (offset 18 in upm RAM) */
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0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
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0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
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/* burst write. (offset 20 in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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/* refresh. (offset 30 in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
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/* exception. (offset 3c in upm RAM) */
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0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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#if !defined(CONFIG_CP850)
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puts ("Board: NC650");
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#else
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puts ("Board: CP850");
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#endif
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#if defined(CONFIG_IDS852_REV1)
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puts (" with IDS852 rev 1 module\n");
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#elif defined(CONFIG_IDS852_REV2)
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puts (" with IDS852 rev 2 module\n");
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#endif
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size8, size9;
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long int size_b0 = 0;
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unsigned long reg;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller bank 1 to the SDRAM bank at
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* preliminary address - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or3 = CFG_OR3_PRELIM;
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memctl->memc_br3 = CFG_BR3_PRELIM;
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memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */
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udelay (200);
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memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */
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udelay (200);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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if (size8 < size9) {
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size_b0 = size9;
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} else {
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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}
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/*
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* Adjust refresh rate depending on SDRAM type, both banks.
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if ((size_b0 < 0x02000000)) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay (1000);
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}
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/*
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* Final mapping
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*/
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memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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udelay (10000);
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/* Configure UPMB for NAND flash access */
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upmconfig (UPMB, (uint *) nand_flash_table,
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sizeof (nand_flash_table) / sizeof (uint));
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memctl->memc_mbmr = CFG_MBMR_NAND;
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base, long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size(base, maxsize));
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}
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#if defined(CONFIG_CP850)
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#define DPRAM_VARNAME "KP850DIP"
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#define PARAM_ADDR 0x7C0
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#define NAME_ADDR 0x7F8
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#define BOARD_NAME "KP01"
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#define DEFAULT_LB "241111"
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int misc_init_r(void)
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{
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int iCompatMode = 0;
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char *pParam = NULL;
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char *envlb;
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/*
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First byte in CPLD read address space signals compatibility mode
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0 - cp850
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1 - kp852
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*/
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pParam = (char*)(CFG_CPLD_BASE);
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if( *pParam != 0)
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iCompatMode = 1;
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if ( iCompatMode != 0) {
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/*
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In KP852 compatibility mode we have to write to
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DPRAM as early as possible the binary coded
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line config and board name.
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The line config is derived from the environment
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variable DPRAM_VARNAME by converting from ASCII
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to binary per character.
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*/
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if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
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setenv( DPRAM_VARNAME, DEFAULT_LB);
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envlb = DEFAULT_LB;
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}
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/* Status string */
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printf("Mode: KP852(LB=%s)\n", envlb);
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/* copy appl init */
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pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
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while (*envlb) {
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*(pParam++) = *(envlb++) - '0';
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}
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*pParam = '\0';
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/* copy board id */
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pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
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strcpy( pParam, BOARD_NAME);
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} else {
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puts("Mode: CP850\n");
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}
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return 0;
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}
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#endif
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