upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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311 lines
6.4 KiB
311 lines
6.4 KiB
/*
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* U-boot - start.S Startup file of u-boot for BF533/BF561
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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*
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* This file is based on head.S
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* Copyright (c) 2003 Metrowerks/Motorola
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* Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
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* Kenneth Albanowski <kjahds@kjahds.com>,
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* The Silver Hammer Group, Ltd.
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* (c) 1995, Dionne & Associates
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* (c) 1995, DKG Display Tech.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/*
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* Note: A change in this file subsequently requires a change in
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* board/$(board_name)/config.mk for a valid u-boot.bin
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*/
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#define ASSEMBLY
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#include <linux/config.h>
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#include <config.h>
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#include <asm/blackfin.h>
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.global _stext;
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.global __bss_start;
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.global start;
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.global _start;
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.global _rambase;
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.global _ramstart;
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.global _ramend;
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.global edata;
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.global _initialize;
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.global _exit;
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.global flashdataend;
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.global init_sdram;
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.text
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_start:
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start:
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_stext:
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R0 = 0x32;
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SYSCFG = R0;
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SSYNC;
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/*
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* As per HW reference manual DAG registers,
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* DATA and Address resgister shall be zero'd
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* in initialization, after a reset state
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*/
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r1 = 0; /* Data registers zero'd */
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r2 = 0;
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r3 = 0;
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r4 = 0;
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r5 = 0;
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r6 = 0;
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r7 = 0;
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p0 = 0; /* Address registers zero'd */
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p1 = 0;
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p2 = 0;
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p3 = 0;
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p4 = 0;
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p5 = 0;
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i0 = 0; /* DAG Registers zero'd */
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i1 = 0;
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i2 = 0;
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i3 = 0;
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m0 = 0;
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m1 = 0;
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m3 = 0;
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m3 = 0;
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l0 = 0;
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l1 = 0;
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l2 = 0;
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l3 = 0;
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b0 = 0;
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b1 = 0;
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b2 = 0;
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b3 = 0;
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/*
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* Set loop counters to zero, to make sure that
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* hw loops are disabled.
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*/
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r0 = 0;
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lc0 = r0;
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lc1 = r0;
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SSYNC;
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/* Check soft reset status */
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p0.h = SWRST >> 16;
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p0.l = SWRST & 0xFFFF;
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r0.l = w[p0];
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cc = bittst(r0, 15);
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if !cc jump no_soft_reset;
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/* Clear Soft reset */
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r0 = 0x0000;
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w[p0] = r0;
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ssync;
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no_soft_reset:
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nop;
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/* Clear EVT registers */
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p0.h = (EVT_EMULATION_ADDR >> 16);
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p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
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p0 += 8;
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p1 = 14;
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r1 = 0;
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LSETUP(4,4) lc0 = p1;
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[ p0 ++ ] = r1;
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p0.h = hi(SIC_IWR);
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p0.l = lo(SIC_IWR);
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r0.l = 0x1;
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w[p0] = r0.l;
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SSYNC;
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sp.l = (0xffb01000 & 0xFFFF);
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sp.h = (0xffb01000 >> 16);
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/*
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* Check if the code is in SDRAM
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* If the code is in SDRAM, skip SDRAM initializaiton
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*/
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call get_pc;
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r3.l = 0x0;
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r3.h = 0x2000;
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cc = r0 < r3 (iu);
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if cc jump sdram_initialized;
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call init_sdram;
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/* relocate into to RAM */
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sdram_initialized:
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call get_pc;
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offset:
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r2.l = offset;
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r2.h = offset;
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r3.l = start;
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r3.h = start;
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r1 = r2 - r3;
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r0 = r0 - r1;
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p1 = r0;
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p2.l = (CFG_MONITOR_BASE & 0xffff);
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p2.h = (CFG_MONITOR_BASE >> 16);
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p3 = 0x04;
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p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
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p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
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loop1:
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r1 = [p1 ++ p3];
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[p2 ++ p3] = r1;
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cc=p2==p4;
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if !cc jump loop1;
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/*
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* configure STACK
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*/
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r0.h = (CONFIG_STACKBASE >> 16);
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r0.l = (CONFIG_STACKBASE & 0xFFFF);
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sp = r0;
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fp = sp;
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/*
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* This next section keeps the processor in supervisor mode
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* during kernel boot. Switches to user mode at end of boot.
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* See page 3-9 of Hardware Reference manual for documentation.
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*/
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/* To keep ourselves in the supervisor mode */
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p0.l = (EVT_IVG15_ADDR & 0xFFFF);
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p0.h = (EVT_IVG15_ADDR >> 16);
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p1.l = _real_start;
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p1.h = _real_start;
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[p0] = p1;
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p0.l = (IMASK & 0xFFFF);
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p0.h = (IMASK >> 16);
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r0.l = LO(IVG15_POS);
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r0.h = HI(IVG15_POS);
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[p0] = r0;
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raise 15;
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p0.l = WAIT_HERE;
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p0.h = WAIT_HERE;
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reti = p0;
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rti;
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WAIT_HERE:
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jump WAIT_HERE;
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.global _real_start;
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_real_start:
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[ -- sp ] = reti;
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#ifdef CONFIG_EZKIT561
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p0.l = (WDOG_CTL & 0xFFFF);
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p0.h = (WDOG_CTL >> 16);
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r0 = WATCHDOG_DISABLE(z);
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w[p0] = r0;
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#endif
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/* DMA reset code to Hi of L1 SRAM */
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copy:
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P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
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P1.L = lo(SYSMMR_BASE);
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R0.H = reset_start; /* Source Address (high) */
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R0.L = reset_start; /* Source Address (low) */
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R1.H = reset_end;
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R1.L = reset_end;
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R2 = R1 - R0; /* Count */
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R1.H = hi(L1_ISRAM); /* Destination Address (high) */
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R1.L = lo(L1_ISRAM); /* Destination Address (low) */
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R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
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R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
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DMA:
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R6 = 0x1 (Z);
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W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
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W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
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[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
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W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
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/* Set Source DMAConfig = DMA Enable,
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Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
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W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
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[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
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W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
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/* Set Destination DMAConfig = DMA Enable,
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Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
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W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
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WAIT_DMA_DONE:
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p0.h = hi(MDMA_D0_IRQ_STATUS);
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p0.l = lo(MDMA_D0_IRQ_STATUS);
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R0 = W[P0](Z);
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CC = BITTST(R0, 0);
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if ! CC jump WAIT_DMA_DONE
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R0 = 0x1;
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W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
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/* Initialize BSS Section with 0 s */
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p1.l = __bss_start;
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p1.h = __bss_start;
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p2.l = _end;
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p2.h = _end;
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r1 = p1;
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r2 = p2;
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r3 = r2 - r1;
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r3 = r3 >> 2;
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p3 = r3;
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lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
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CC = p2<=p1;
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if CC jump _clear_bss_skip;
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r0 = 0;
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_clear_bss:
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_clear_bss_end:
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[p1++] = r0;
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_clear_bss_skip:
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p0.l = _start1;
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p0.h = _start1;
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jump (p0);
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reset_start:
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p0.h = WDOG_CNT >> 16;
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p0.l = WDOG_CNT & 0xffff;
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r0 = 0x0010;
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w[p0] = r0;
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p0.h = WDOG_CTL >> 16;
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p0.l = WDOG_CTL & 0xffff;
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r0 = 0x0000;
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w[p0] = r0;
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reset_wait:
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jump reset_wait;
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reset_end: nop;
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_exit:
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jump.s _exit;
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get_pc:
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r0 = rets;
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rts;
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