upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
337 lines
9.0 KiB
337 lines
9.0 KiB
/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#if defined(CONFIG_CMD_NET)
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#include <config.h>
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#include <net.h>
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#include <asm/fec.h>
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#endif
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#ifdef CONFIG_MCF5301x
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void cpu_init_f(void)
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{
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volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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/* watchdog is enabled by default - disable the watchdog */
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#ifndef CONFIG_WATCHDOG
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/*wdog->cr = 0; */
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#endif
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scm1->mpr = 0x77777777;
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scm1->pacra = 0;
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scm1->pacrb = 0;
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scm1->pacrc = 0;
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scm1->pacrd = 0;
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scm1->pacre = 0;
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scm1->pacrf = 0;
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scm1->pacrg = 0;
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
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&& defined(CONFIG_SYS_CS0_CTRL))
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gpio->par_cs |= GPIO_PAR_CS0_CS0;
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fbcs->csar0 = CONFIG_SYS_CS0_BASE;
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fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
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fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
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&& defined(CONFIG_SYS_CS1_CTRL))
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gpio->par_cs |= GPIO_PAR_CS1_CS1;
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fbcs->csar1 = CONFIG_SYS_CS1_BASE;
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fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
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fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
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&& defined(CONFIG_SYS_CS2_CTRL))
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fbcs->csar2 = CONFIG_SYS_CS2_BASE;
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fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
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fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
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&& defined(CONFIG_SYS_CS3_CTRL))
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fbcs->csar3 = CONFIG_SYS_CS3_BASE;
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fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
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fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
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&& defined(CONFIG_SYS_CS4_CTRL))
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gpio->par_cs |= GPIO_PAR_CS4;
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fbcs->csar4 = CONFIG_SYS_CS4_BASE;
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fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
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fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
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&& defined(CONFIG_SYS_CS5_CTRL))
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gpio->par_cs |= GPIO_PAR_CS5;
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fbcs->csar5 = CONFIG_SYS_CS5_BASE;
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fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
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fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
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#endif
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#ifdef CONFIG_FSL_I2C
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gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
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#endif
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icache_enable();
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}
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/* initialize higher level parts of CPU like timers */
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int cpu_init_r(void)
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{
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#ifdef CONFIG_MCFFEC
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volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
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#endif
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#ifdef CONFIG_MCFRTC
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volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
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volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
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rtcex->gocu = CONFIG_SYS_RTC_CNT;
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rtcex->gocl = CONFIG_SYS_RTC_SETUP;
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#endif
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#ifdef CONFIG_MCFFEC
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if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
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ccm->misccr |= CCM_MISCCR_FECM;
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else
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ccm->misccr &= ~CCM_MISCCR_FECM;
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#endif
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (CONFIG_SYS_UART_PORT) {
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case 0:
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gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
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break;
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case 1:
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#ifdef CONFIG_SYS_UART1_ALT1_GPIO
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gpio->par_simp1h &=
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~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
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gpio->par_simp1h |=
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(GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
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#elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
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gpio->par_ssih &=
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~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
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gpio->par_ssih |=
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(GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
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#endif
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break;
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case 2:
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#ifdef CONFIG_SYS_UART2_PRI_GPIO
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gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
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#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
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gpio->par_dspih &=
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~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
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gpio->par_dspih |=
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(GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
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#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
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gpio->par_feci2c &=
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~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
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gpio->par_feci2c |=
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(GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
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#endif
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break;
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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struct fec_info_s *info = (struct fec_info_s *)dev->priv;
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if (setclear) {
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
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gpio->par_fec |=
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GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
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gpio->par_feci2c |=
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GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
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} else {
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gpio->par_fec |=
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GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
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gpio->par_feci2c |=
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GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
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}
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} else {
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if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
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gpio->par_fec &=
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~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
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gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
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} else {
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gpio->par_fec &=
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~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
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gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
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}
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}
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return 0;
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}
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#endif /* CONFIG_CMD_NET */
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#endif /* CONFIG_MCF5301x */
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#ifdef CONFIG_MCF532x
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void cpu_init_f(void)
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{
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volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
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volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
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/* watchdog is enabled by default - disable the watchdog */
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#ifndef CONFIG_WATCHDOG
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wdog->cr = 0;
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#endif
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scm1->mpr0 = 0x77777777;
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scm2->pacra = 0;
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scm2->pacrb = 0;
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scm2->pacrc = 0;
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scm2->pacrd = 0;
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scm2->pacre = 0;
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scm2->pacrf = 0;
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scm2->pacrg = 0;
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scm1->pacrh = 0;
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/* Port configuration */
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gpio->par_cs = 0;
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#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
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&& defined(CONFIG_SYS_CS0_CTRL))
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fbcs->csar0 = CONFIG_SYS_CS0_BASE;
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fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
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fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
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&& defined(CONFIG_SYS_CS1_CTRL))
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/* Latch chipselect */
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gpio->par_cs |= GPIO_PAR_CS1;
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fbcs->csar1 = CONFIG_SYS_CS1_BASE;
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fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
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fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
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&& defined(CONFIG_SYS_CS2_CTRL))
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gpio->par_cs |= GPIO_PAR_CS2;
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fbcs->csar2 = CONFIG_SYS_CS2_BASE;
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fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
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fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
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&& defined(CONFIG_SYS_CS3_CTRL))
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gpio->par_cs |= GPIO_PAR_CS3;
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fbcs->csar3 = CONFIG_SYS_CS3_BASE;
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fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
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fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
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&& defined(CONFIG_SYS_CS4_CTRL))
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gpio->par_cs |= GPIO_PAR_CS4;
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fbcs->csar4 = CONFIG_SYS_CS4_BASE;
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fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
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fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
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&& defined(CONFIG_SYS_CS5_CTRL))
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gpio->par_cs |= GPIO_PAR_CS5;
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fbcs->csar5 = CONFIG_SYS_CS5_BASE;
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fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
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fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
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#endif
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#ifdef CONFIG_FSL_I2C
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gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
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#endif
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(void)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (CONFIG_SYS_UART_PORT) {
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case 0:
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gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
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break;
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case 1:
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gpio->par_uart =
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(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
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break;
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case 2:
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gpio->par_timer &= 0x0F;
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gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
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break;
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(struct eth_device *dev, int setclear)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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if (setclear) {
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gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
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gpio->par_feci2c |=
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GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
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} else {
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gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
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gpio->par_feci2c &=
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~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
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}
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return 0;
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}
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#endif
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#endif /* CONFIG_MCF532x */
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