upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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373 lines
9.2 KiB
373 lines
9.2 KiB
/*
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* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
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* Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device.h>
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#include <generic-phy.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <syscon.h>
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#include <regmap.h>
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/* PLLCTRL Registers */
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#define PLL_STATUS 0x00000004
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#define PLL_GO 0x00000008
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#define PLL_CONFIGURATION1 0x0000000C
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#define PLL_CONFIGURATION2 0x00000010
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#define PLL_CONFIGURATION3 0x00000014
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#define PLL_CONFIGURATION4 0x00000020
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#define PLL_REGM_MASK 0x001FFE00
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#define PLL_REGM_SHIFT 9
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#define PLL_REGM_F_MASK 0x0003FFFF
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#define PLL_REGM_F_SHIFT 0
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#define PLL_REGN_MASK 0x000001FE
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#define PLL_REGN_SHIFT 1
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#define PLL_SELFREQDCO_MASK 0x0000000E
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#define PLL_SELFREQDCO_SHIFT 1
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#define PLL_SD_MASK 0x0003FC00
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#define PLL_SD_SHIFT 10
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#define SET_PLL_GO 0x1
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#define PLL_TICOPWDN BIT(16)
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#define PLL_LDOPWDN BIT(15)
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#define PLL_LOCK 0x2
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#define PLL_IDLE 0x1
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/* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
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#define SATA_PLL_SOFT_RESET (1<<18)
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/* PHY POWER CONTROL Register */
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
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#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
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#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
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#define PLL_IDLE_TIME 100 /* in milliseconds */
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#define PLL_LOCK_TIME 100 /* in milliseconds */
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struct omap_pipe3 {
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void __iomem *pll_ctrl_base;
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void __iomem *power_reg;
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void __iomem *pll_reset_reg;
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struct pipe3_dpll_map *dpll_map;
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};
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struct pipe3_dpll_params {
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u16 m;
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u8 n;
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u8 freq:3;
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u8 sd;
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u32 mf;
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};
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struct pipe3_dpll_map {
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unsigned long rate;
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struct pipe3_dpll_params params;
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};
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static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
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{
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return readl(addr + offset);
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}
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static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
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u32 data)
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{
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writel(data, addr + offset);
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}
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static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
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*pipe3)
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{
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u32 rate;
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struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
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rate = get_sys_clk_freq();
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for (; dpll_map->rate; dpll_map++) {
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if (rate == dpll_map->rate)
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return &dpll_map->params;
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}
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printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
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__func__, rate);
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return NULL;
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}
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static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
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{
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u32 val;
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int timeout = PLL_LOCK_TIME;
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do {
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mdelay(1);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
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if (val & PLL_LOCK)
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break;
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} while (--timeout);
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if (!(val & PLL_LOCK)) {
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printf("%s: DPLL failed to lock\n", __func__);
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return -EBUSY;
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}
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return 0;
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}
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static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
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{
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u32 val;
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struct pipe3_dpll_params *dpll_params;
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dpll_params = omap_pipe3_get_dpll_params(pipe3);
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if (!dpll_params) {
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printf("%s: Invalid DPLL parameters\n", __func__);
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return -EINVAL;
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}
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGN_MASK;
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val |= dpll_params->n << PLL_REGN_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
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val &= ~PLL_SELFREQDCO_MASK;
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val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGM_MASK;
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val |= dpll_params->m << PLL_REGM_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
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val &= ~PLL_REGM_F_MASK;
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val |= dpll_params->mf << PLL_REGM_F_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
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val &= ~PLL_SD_MASK;
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val |= dpll_params->sd << PLL_SD_SHIFT;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
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return omap_pipe3_wait_lock(pipe3);
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}
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static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
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{
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u32 val, rate;
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val = readl(pipe3->power_reg);
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rate = get_sys_clk_freq();
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rate = rate/1000000;
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if (on) {
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val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
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val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
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val |= rate <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
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} else {
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val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
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val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
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OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
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}
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writel(val, pipe3->power_reg);
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}
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static int pipe3_init(struct phy *phy)
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{
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int ret;
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u32 val;
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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/* Program the DPLL only if not locked */
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
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if (!(val & PLL_LOCK)) {
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ret = omap_pipe3_dpll_program(pipe3);
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if (ret)
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return ret;
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} else {
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/* else just bring it out of IDLE mode */
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val = omap_pipe3_readl(pipe3->pll_ctrl_base,
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PLL_CONFIGURATION2);
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if (val & PLL_IDLE) {
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val &= ~PLL_IDLE;
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omap_pipe3_writel(pipe3->pll_ctrl_base,
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PLL_CONFIGURATION2, val);
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ret = omap_pipe3_wait_lock(pipe3);
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if (ret)
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return ret;
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}
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}
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return 0;
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}
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static int pipe3_power_on(struct phy *phy)
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{
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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/* Power up the PHY */
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omap_control_pipe3_power(pipe3, 1);
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return 0;
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}
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static int pipe3_power_off(struct phy *phy)
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{
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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/* Power down the PHY */
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omap_control_pipe3_power(pipe3, 0);
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return 0;
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}
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static int pipe3_exit(struct phy *phy)
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{
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u32 val;
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int timeout = PLL_IDLE_TIME;
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struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
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pipe3_power_off(phy);
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/* Put DPLL in IDLE mode */
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
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val |= PLL_IDLE;
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omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
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/* wait for LDO and Oscillator to power down */
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do {
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mdelay(1);
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val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
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if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
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break;
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} while (--timeout);
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if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
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error("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
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__func__, val);
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return -EBUSY;
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}
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val = readl(pipe3->pll_reset_reg);
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writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
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mdelay(1);
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writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
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return 0;
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}
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static void *get_reg(struct udevice *dev, const char *name)
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{
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struct udevice *syscon;
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struct regmap *regmap;
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const fdt32_t *cell;
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int len, err;
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void *base;
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err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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name, &syscon);
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if (err) {
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error("unable to find syscon device for %s (%d)\n",
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name, err);
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return NULL;
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}
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regmap = syscon_get_regmap(syscon);
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if (IS_ERR(regmap)) {
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error("unable to find regmap for %s (%ld)\n",
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name, PTR_ERR(regmap));
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return NULL;
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}
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cell = fdt_getprop(gd->fdt_blob, dev->of_offset, name,
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&len);
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if (len < 2*sizeof(fdt32_t)) {
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error("offset not available for %s\n", name);
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return NULL;
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}
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base = regmap_get_range(regmap, 0);
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if (!base)
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return NULL;
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return fdtdec_get_number(cell + 1, 1) + base;
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}
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static int pipe3_phy_probe(struct udevice *dev)
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{
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fdt_addr_t addr;
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fdt_size_t sz;
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struct omap_pipe3 *pipe3 = dev_get_priv(dev);
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addr = dev_get_addr_size_index(dev, 2, &sz);
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if (addr == FDT_ADDR_T_NONE) {
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error("missing pll ctrl address\n");
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return -EINVAL;
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}
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pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
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if (!pipe3->pll_ctrl_base) {
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error("unable to remap pll ctrl\n");
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return -EINVAL;
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}
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pipe3->power_reg = get_reg(dev, "syscon-phy-power");
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if (!pipe3->power_reg)
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return -EINVAL;
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pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
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if (!pipe3->pll_reset_reg)
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return -EINVAL;
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pipe3->dpll_map = (struct pipe3_dpll_map *)dev_get_driver_data(dev);
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return 0;
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}
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static struct pipe3_dpll_map dpll_map_sata[] = {
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{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
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{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
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{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
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{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
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{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
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{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
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{ }, /* Terminator */
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};
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static const struct udevice_id pipe3_phy_ids[] = {
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{ .compatible = "ti,phy-pipe3-sata", .data = (ulong)&dpll_map_sata },
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{ }
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};
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static struct phy_ops pipe3_phy_ops = {
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.init = pipe3_init,
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.power_on = pipe3_power_on,
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.power_off = pipe3_power_off,
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.exit = pipe3_exit,
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};
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U_BOOT_DRIVER(pipe3_phy) = {
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.name = "pipe3_phy",
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.id = UCLASS_PHY,
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.of_match = pipe3_phy_ids,
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.ops = &pipe3_phy_ops,
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.probe = pipe3_phy_probe,
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.priv_auto_alloc_size = sizeof(struct omap_pipe3),
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};
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