upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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35 lines
1.1 KiB
35 lines
1.1 KiB
* Synopsys HSDK clock generation unit
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The Synopsys HSDK clock controller generates and supplies clock to various
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controllers and peripherals within the SoC.
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Required Properties:
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- compatible: should be "snps,hsdk-cgu-clock"
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- reg: the pair of physical base address and length of clock generation unit
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memory mapped region and creg arc core divider memory mapped region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be
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used in device tree sources.
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Example: Clock controller node:
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cgu_clk: cgu-clk@f0000000 {
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compatible = "snps,hsdk-cgu-clock";
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reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>;
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#clock-cells = <1>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart0: serial0@f0005000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xf0005000 0x1000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cgu_clk CLK_SYS_UART_REF>;
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};
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