upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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298 lines
8.6 KiB
298 lines
8.6 KiB
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
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* Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PCH_GBE_H_
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#define _PCH_GBE_H_
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#define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define PCH_GBE_DESC_NUM 4
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#define PCH_GBE_ALIGN_SIZE 64
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/*
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* Topcliff GBE MAC supports receiving ethernet frames with normal frame size
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* (64-1518 bytes) as well as up to 10318 bytes, however it does not have a
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* register bit to turn off receiving 'jumbo frame', so we have to allocate
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* our own buffer to store the received frames instead of using U-Boot's own.
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*/
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#define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE)
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/* Interrupt Status */
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/* Interrupt Status Hold */
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/* Interrupt Enable */
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#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001
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#define PCH_GBE_INT_RX_VALID 0x00000002
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#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004
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#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008
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#define PCH_GBE_INT_RX_DMA_ERR 0x00000010
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#define PCH_GBE_INT_RX_DSC_EMP 0x00000020
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#define PCH_GBE_INT_TX_CMPLT 0x00000100
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#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200
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#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400
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#define PCH_GBE_INT_TX_DMA_ERR 0x00000800
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#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000
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#define PCH_GBE_INT_MIIM_CMPLT 0x00010000
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#define PCH_GBE_INT_PHY_INT 0x00100000
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#define PCH_GBE_INT_WOL_DET 0x01000000
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#define PCH_GBE_INT_TCPIP_ERR 0x10000000
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/* Mode */
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#define PCH_GBE_MODE_MII_ETHER 0x00000000
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#define PCH_GBE_MODE_GMII_ETHER 0x80000000
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#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000
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#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000
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#define PCH_GBE_MODE_FR_BST 0x04000000
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/* Reset */
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#define PCH_GBE_ALL_RST 0x80000000
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#define PCH_GBE_TX_RST 0x00008000
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#define PCH_GBE_RX_RST 0x00004000
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/* TCP/IP Accelerator Control */
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#define PCH_GBE_EX_LIST_EN 0x00000008
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#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004
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#define PCH_GBE_TX_TCPIPACC_EN 0x00000002
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#define PCH_GBE_RX_TCPIPACC_EN 0x00000001
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/* MAC RX Enable */
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#define PCH_GBE_MRE_MAC_RX_EN 0x00000001
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/* RX Flow Control */
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#define PCH_GBE_FL_CTRL_EN 0x80000000
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/* RX Mode */
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#define PCH_GBE_ADD_FIL_EN 0x80000000
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#define PCH_GBE_MLT_FIL_EN 0x40000000
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#define PCH_GBE_RH_ALM_EMP_4 0x00000000
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#define PCH_GBE_RH_ALM_EMP_8 0x00004000
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#define PCH_GBE_RH_ALM_EMP_16 0x00008000
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#define PCH_GBE_RH_ALM_EMP_32 0x0000c000
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#define PCH_GBE_RH_ALM_FULL_4 0x00000000
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#define PCH_GBE_RH_ALM_FULL_8 0x00001000
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#define PCH_GBE_RH_ALM_FULL_16 0x00002000
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#define PCH_GBE_RH_ALM_FULL_32 0x00003000
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#define PCH_GBE_RH_RD_TRG_4 0x00000000
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#define PCH_GBE_RH_RD_TRG_8 0x00000200
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#define PCH_GBE_RH_RD_TRG_16 0x00000400
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#define PCH_GBE_RH_RD_TRG_32 0x00000600
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#define PCH_GBE_RH_RD_TRG_64 0x00000800
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#define PCH_GBE_RH_RD_TRG_128 0x00000a00
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#define PCH_GBE_RH_RD_TRG_256 0x00000c00
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#define PCH_GBE_RH_RD_TRG_512 0x00000e00
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/* TX Mode */
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#define PCH_GBE_TM_NO_RTRY 0x80000000
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#define PCH_GBE_TM_LONG_PKT 0x40000000
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#define PCH_GBE_TM_ST_AND_FD 0x20000000
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#define PCH_GBE_TM_SHORT_PKT 0x10000000
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#define PCH_GBE_TM_LTCOL_RETX 0x08000000
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#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000
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#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000
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#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000
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#define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000
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#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000
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#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800
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#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000
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#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800
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#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000
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#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800
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#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000
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#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800
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#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000
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#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200
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#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400
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#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600
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/* MAC Address Mask */
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#define PCH_GBE_BUSY 0x80000000
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/* MIIM */
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#define PCH_GBE_MIIM_OPER_WRITE 0x04000000
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#define PCH_GBE_MIIM_OPER_READ 0x00000000
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#define PCH_GBE_MIIM_OPER_READY 0x04000000
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#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
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#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
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/* RGMII Control */
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#define PCH_GBE_CRS_SEL 0x00000010
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#define PCH_GBE_RGMII_RATE_125M 0x00000000
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#define PCH_GBE_RGMII_RATE_25M 0x00000008
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#define PCH_GBE_RGMII_RATE_2_5M 0x0000000c
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#define PCH_GBE_RGMII_MODE_GMII 0x00000000
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#define PCH_GBE_RGMII_MODE_RGMII 0x00000002
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#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
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#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
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/* DMA Control */
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#define PCH_GBE_RX_DMA_EN 0x00000002
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#define PCH_GBE_TX_DMA_EN 0x00000001
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/* Receive Descriptor bit definitions */
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#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
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#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
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#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
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#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0
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#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
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#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
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#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
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#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
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#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
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#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
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#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
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#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
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#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
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#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
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#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
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#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
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#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
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#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
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#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
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#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
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#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
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#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
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/* Transmit Descriptor bit definitions */
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#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
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#define PCH_GBE_TXD_CTRL_ITAG 0x0004
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#define PCH_GBE_TXD_CTRL_ICRC 0x0002
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#define PCH_GBE_TXD_CTRL_APAD 0x0001
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#define PCH_GBE_TXD_WORDS_SHIFT 2
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#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
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#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
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#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
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#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
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#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
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#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
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#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
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#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
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#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
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#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
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/**
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* struct pch_gbe_rx_desc - Receive Descriptor
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* @buffer_addr: RX Frame Buffer Address
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* @tcp_ip_status: TCP/IP Accelerator Status
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* @rx_words_eob: RX word count and Byte position
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* @gbec_status: GMAC Status
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* @dma_status: DMA Status
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* @reserved1: Reserved
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* @reserved2: Reserved
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*/
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struct pch_gbe_rx_desc {
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u32 buffer_addr;
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u32 tcp_ip_status;
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u16 rx_words_eob;
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u16 gbec_status;
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u8 dma_status;
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u8 reserved1;
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u16 reserved2;
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};
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/**
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* struct pch_gbe_tx_desc - Transmit Descriptor
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* @buffer_addr: TX Frame Buffer Address
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* @length: Data buffer length
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* @reserved1: Reserved
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* @tx_words_eob: TX word count and Byte position
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* @tx_frame_ctrl: TX Frame Control
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* @dma_status: DMA Status
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* @reserved2: Reserved
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* @gbec_status: GMAC Status
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*/
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struct pch_gbe_tx_desc {
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u32 buffer_addr;
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u16 length;
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u16 reserved1;
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u16 tx_words_eob;
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u16 tx_frame_ctrl;
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u8 dma_status;
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u8 reserved2;
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u16 gbec_status;
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};
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/**
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* pch_gbe_regs_mac_adr - structure holding values of mac address registers
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*
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* @high Denotes the 1st to 4th byte from the initial of MAC address
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* @low Denotes the 5th to 6th byte from the initial of MAC address
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*/
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struct pch_gbe_regs_mac_adr {
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u32 high;
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u32 low;
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};
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/**
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* pch_gbe_regs - structure holding values of MAC registers
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*/
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struct pch_gbe_regs {
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u32 int_st;
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u32 int_en;
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u32 mode;
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u32 reset;
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u32 tcpip_acc;
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u32 ex_list;
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u32 int_st_hold;
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u32 phy_int_ctrl;
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u32 mac_rx_en;
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u32 rx_fctrl;
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u32 pause_req;
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u32 rx_mode;
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u32 tx_mode;
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u32 rx_fifo_st;
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u32 tx_fifo_st;
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u32 tx_fid;
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u32 tx_result;
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u32 pause_pkt1;
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u32 pause_pkt2;
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u32 pause_pkt3;
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u32 pause_pkt4;
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u32 pause_pkt5;
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u32 reserve[2];
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struct pch_gbe_regs_mac_adr mac_adr[16];
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u32 addr_mask;
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u32 miim;
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u32 mac_addr_load;
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u32 rgmii_st;
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u32 rgmii_ctrl;
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u32 reserve3[3];
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u32 dma_ctrl;
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u32 reserve4[3];
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u32 rx_dsc_base;
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u32 rx_dsc_size;
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u32 rx_dsc_hw_p;
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u32 rx_dsc_hw_p_hld;
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u32 rx_dsc_sw_p;
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u32 reserve5[3];
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u32 tx_dsc_base;
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u32 tx_dsc_size;
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u32 tx_dsc_hw_p;
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u32 tx_dsc_hw_p_hld;
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u32 tx_dsc_sw_p;
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u32 reserve6[3];
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u32 rx_dma_st;
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u32 tx_dma_st;
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u32 reserve7[2];
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u32 wol_st;
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u32 wol_ctrl;
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u32 wol_addr_mask;
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};
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struct pch_gbe_priv {
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struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM];
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struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM];
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char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN];
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struct phy_device *phydev;
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struct mii_dev *bus;
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struct pch_gbe_regs *mac_regs;
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pci_dev_t bdf;
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int rx_idx;
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int tx_idx;
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};
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#endif /* _PCH_GBE_H_ */
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