upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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430 lines
14 KiB
430 lines
14 KiB
/*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2006
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* Eric Schumann, Phytec Messatechnik GmbH
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*
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* (C) Copyright 2009
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* Jon Smirl <jonsmirl@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
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#define CONFIG_SYS_GENERIC_BOARD
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/*-----------------------------------------------------------------------------
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High Level Configuration Options
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(easy to change)
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-----------------------------------------------------------------------------*/
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#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
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#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
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#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
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/* FEC configuration and IDE */
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/*
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* Valid values for CONFIG_SYS_TEXT_BASE are:
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* 0xFFF00000 boot high (standard configuration)
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* 0xFF000000 boot low
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* 0x00100000 boot from RAM (for testing only)
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*/
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#endif
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#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
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/*-----------------------------------------------------------------------------
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Serial console configuration
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-----------------------------------------------------------------------------*/
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#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
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/*define gps port conf. */
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/* register later on to */
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/*enable UART function! */
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PCI
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#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
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#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
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#define CONFIG_SYS_LOWBOOT 1
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#endif
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/* RAMBOOT will be defined automatically in memory section */
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
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#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
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"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
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/*-----------------------------------------------------------------------------
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Autobooting
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-----------------------------------------------------------------------------*/
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
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/* even with bootdelay=0 */
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#undef CONFIG_BOOTARGS
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
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"mount root filesystem over NFS;" \
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"echo"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uimage=uImage-pcm030\0" \
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"oftree=oftree-pcm030.dtb\0" \
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"jffs2=root-pcm030.jffs2\0" \
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"uboot=u-boot-pcm030.bin\0" \
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"bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
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" $(mtdparts) rw\0" \
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"bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
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" rootfstype=jffs2\0" \
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"bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
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" ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
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"$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
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" tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
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"bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
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"0xfff40000\0" \
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" cp.b 0x400000 0xff040000 $(filesize)\0" \
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"prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
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"cp.b 0x400000 0xff200000 $(filesize)\0" \
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"prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
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" cp.b 0x400000 0xfff40000 $(filesize)\0" \
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"update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
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" cp.b 0x400000 0xFFF00000 $(filesize)\0" \
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"unlock=yes\0" \
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""
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#define CONFIG_BOOTCOMMAND "run bcmd_flash"
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/*--------------------------------------------------------------------------
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IPB Bus clocking configuration.
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---------------------------------------------------------------------------*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*-------------------------------------------------------------------------
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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* -----------------------------------------------------------------------*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_SYS_XLB_PIPELINING 1
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/*---------------------------------------------------------------------------
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I2C configuration
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---------------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*---------------------------------------------------------------------------
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EEPROM CAT24WC32 configuration
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---------------------------------------------------------------------------*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
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#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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#define CONFIG_SYS_EEPROM_SIZE 2048
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
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/*---------------------------------------------------------------------------
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RTC configuration
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---------------------------------------------------------------------------*/
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#define RTC
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#define CONFIG_RTC_PCF8563 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*---------------------------------------------------------------------------
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Flash configuration
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---------------------------------------------------------------------------*/
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#define CONFIG_SYS_FLASH_BASE 0xff000000
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#define CONFIG_SYS_FLASH_SIZE 0x01000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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/* (= chip selects) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/*
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* Use also hardware protection. This seems required, as the BDI uses
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* hardware protection. Without this, U-Boot can't work with this sectors,
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* as its protection is software only by default
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*/
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#define CONFIG_SYS_FLASH_PROTECTION 1
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/*---------------------------------------------------------------------------
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Environment settings
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---------------------------------------------------------------------------*/
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/* pcm030 ships with environment is EEPROM by default */
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#define CONFIG_ENV_IS_IN_EEPROM 1
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#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
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/*beginning of the EEPROM */
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#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
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#define CONFIG_ENV_OVERWRITE 1
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/*-----------------------------------------------------------------------------
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Memory map
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-----------------------------------------------------------------------------*/
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#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
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/* bootloader or debugger config */
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used */
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/* area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------------
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Ethernet configuration
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-----------------------------------------------------------------------------*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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#define CONFIG_PHY_ADDR 0x01
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/*---------------------------------------------------------------------------
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GPIO configuration
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---------------------------------------------------------------------------*/
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/* GPIO port configuration
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*
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* Pin mapping:
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*
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* [29:31] = 01x
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* PSC1_0 -> AC97 SDATA out
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* PSC1_1 -> AC97 SDTA in
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* PSC1_2 -> AC97 SYNC out
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* PSC1_3 -> AC97 bitclock out
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* PSC1_4 -> AC97 reset out
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*
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* [25:27] = 001
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* PSC2_0 -> CAN 1 Tx out
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* PSC2_1 -> CAN 1 Rx in
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* PSC2_2 -> CAN 2 Tx out
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* PSC2_3 -> CAN 2 Rx in
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* PSC2_4 -> GPIO (claimed for ATA reset, active low)
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*
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*
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* [20:23] = 1100
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* PSC3_0 -> UART Tx out
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* PSC3_1 -> UART Rx in
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* PSC3_2 -> UART RTS (in/out FIXME)
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* PSC3_3 -> UART CTS (in/out FIXME)
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* PSC3_4 -> LocalPlus Bus CS6 \
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* PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
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* PSC3_6 -> dedicated SPI MOSI out (master case)
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* PSC3_7 -> dedicated SPI MISO in (master case)
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* PSC3_8 -> dedicated SPI SS out (master case)
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* PSC3_9 -> dedicated SPI CLK out (master case)
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*
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* [18:19] = 01
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* USB_0 -> USB OE out
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* USB_1 -> USB Tx- out
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* USB_2 -> USB Tx+ out
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* USB_3 -> USB RxD (in/out FIXME)
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* USB_4 -> USB Rx+ in
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* USB_5 -> USB Rx- in
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* USB_6 -> USB PortPower out
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* USB_7 -> USB speed out
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* USB_8 -> USB suspend (in/out FIXME)
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* USB_9 -> USB overcurrent in
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*
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* [17] = 0
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* USB differential mode
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*
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* [16] = 0
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* PCI enabled
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*
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* [12:15] = 0101
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* ETH_0 -> ETH Txen
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* ETH_1 -> ETH TxD0
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* ETH_2 -> ETH TxD1
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* ETH_3 -> ETH TxD2
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* ETH_4 -> ETH TxD3
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* ETH_5 -> ETH Txerr
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* ETH_6 -> ETH MDC
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* ETH_7 -> ETH MDIO
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* ETH_8 -> ETH RxDv
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* ETH_9 -> ETH RxCLK
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* ETH_10 -> ETH Collision
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* ETH_11 -> ETH TxD
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* ETH_12 -> ETH RxD0
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* ETH_13 -> ETH RxD1
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* ETH_14 -> ETH RxD2
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* ETH_15 -> ETH RxD3
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* ETH_16 -> ETH Rxerr
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* ETH_17 -> ETH CRS
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*
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* [9:11] = 101
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* PSC6_0 -> UART RxD in
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* PSC6_1 -> UART CTS (in/out FIXME)
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* PSC6_2 -> UART TxD out
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* PSC6_3 -> UART RTS (in/out FIXME)
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*
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* [2:3/6:7] = 00/11
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* TMR_0 -> ATA_CS0 out
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* TMR_1 -> ATA_CS1 out
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* TMR_2 -> GPIO
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* TMR_3 -> GPIO
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* TMR_4 -> GPIO
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* TMR_5 -> GPIO
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* TMR_6 -> GPIO
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* TMR_7 -> GPIO
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* I2C_0 -> I2C 1 Clock out
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* I2C_1 -> I2C 1 IO in/out
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* I2C_2 -> I2C 2 Clock out
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* I2C_3 -> I2C 2 IO in/out
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*
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* [4] = 1
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* PSC3_5 is used as CS7
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*
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* [5] = 1
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* PSC3_4 is used as CS6
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*
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* [1] = 0
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* gpio_wkup_7 is GPIO
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*
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* [0] = 0
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* gpio_wkup_6 is GPIO
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*
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
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/*-----------------------------------------------------------------------------
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Miscellaneous configurable options
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-------------------------------------------------------------------------------*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
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#define CONFIG_DISPLAY_BOARDINFO 1
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/*-----------------------------------------------------------------------------
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Various low-level settings
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-----------------------------------------------------------------------------*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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/* no burst access on the LPB */
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#define CONFIG_SYS_CS_BURST 0x00000000
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/* one deadcycle for the 33MHz statemachine */
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
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/* one additional waitstate for the 33MHz statemachine */
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#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00001000
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/*---------------------------------------------------------------------------
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IDE/ATA stuff Supports IDE harddisk
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----------------------------------------------------------------------------*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_SYS_ATA_CS_ON_TIMER01
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#define CONFIG_IDE_RESET 1 /* reset for ide supported */
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CONFIG_SYS_ATA_STRIDE 4
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#define CONFIG_ATAPI 1
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/* we enable IDE and FAT support, so we also need partition support */
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#define CONFIG_DOS_PARTITION 1
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/* USB */
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_STORAGE
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_CPU "PowerPC,5200@0"
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#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
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#define OF_SOC "soc5200@f0000000"
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#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
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#endif /* __CONFIG_H */
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