upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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711 lines
20 KiB
711 lines
20 KiB
/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx51_pins.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <mxc_gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/errno.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <fsl_pmic.h>
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#include <mc13892.h>
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DECLARE_GLOBAL_DATA_PTR;
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static u32 system_rev;
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#ifdef CONFIG_HW_WATCHDOG
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#include <watchdog.h>
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void hw_watchdog_reset(void)
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{
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int val;
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/* toggle watchdog trigger pin */
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val = mxc_gpio_get(66);
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val = val ? 0 : 1;
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mxc_gpio_set(66, val);
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}
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#endif
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static void init_drive_strength(void)
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{
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
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mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
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/* Setting pad options */
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
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PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
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PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
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}
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u32 get_board_rev(void)
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{
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system_rev = get_cpu_rev();
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return system_rev;
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}
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int dram_init(void)
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{
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#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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#if (CONFIG_NR_DRAM_BANKS > 1)
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
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PHYS_SDRAM_2_SIZE);
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#endif
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#else
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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#endif
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return 0;
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}
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static void setup_weim(void)
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{
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struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
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pweim->csgcr1 = 0x004100b9;
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pweim->csgcr2 = 0x00000001;
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pweim->csrcr1 = 0x0a018000;
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pweim->csrcr2 = 0;
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pweim->cswcr1 = 0x0704a240;
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}
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static void setup_uart(void)
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{
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unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
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/* console RX on Pin EIM_D25 */
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mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad);
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/* console TX on Pin EIM_D26 */
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mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad);
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}
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#ifdef CONFIG_MXC_SPI
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void spi_io_init(void)
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{
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/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
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mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/*
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* SS1 will be used as GPIO because of uninterrupted
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* long SPI transmissions (GPIO4_25)
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*/
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mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7);
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mxc_iomux_set_pad(MX51_PIN_DI1_PIN11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
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mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
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}
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static void reset_peripherals(int reset)
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{
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if (reset) {
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/* reset_n is on NANDF_D15 */
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mxc_gpio_set(89, 0);
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mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT);
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#ifdef CONFIG_VISION2_HW_1_0
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/*
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* set FEC Configuration lines
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* set levels of FEC config lines
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*/
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mxc_gpio_set(75, 0);
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mxc_gpio_set(74, 1);
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mxc_gpio_set(95, 1);
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mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT);
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/* set direction of FEC config lines */
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mxc_gpio_set(59, 0);
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mxc_gpio_set(60, 0);
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mxc_gpio_set(61, 0);
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mxc_gpio_set(55, 1);
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mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT);
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/* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */
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mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
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/* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */
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mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1);
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/* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */
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mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1);
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/* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */
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mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1);
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/* FEC_COL - sel GPIO (3-10) for configuration -> 1 */
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mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3);
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/* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */
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mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3);
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/* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */
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mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3);
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#endif
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/*
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* activate reset_n pin
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* Select mux mode: ALT3 mux port: NAND D15
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*/
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mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D15,
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PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX);
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} else {
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/* set FEC Control lines */
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mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN);
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udelay(500);
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#ifdef CONFIG_VISION2_HW_1_0
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/* FEC RDATA[3] */
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mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
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/* FEC RDATA[2] */
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mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
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/* FEC RDATA[1] */
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mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
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/* FEC RDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
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/* FEC RX_CLK */
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mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
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/* FEC RX_ER */
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mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
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/* FEC COL */
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mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
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#endif
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}
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}
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static void power_init_mx51(void)
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{
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unsigned int val;
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/* Write needed to Power Gate 2 register */
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val = pmic_reg_read(REG_POWER_MISC);
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/* enable VCAM with 2.775V to enable read from PMIC */
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val = VCAMCONFIG | VCAMEN;
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pmic_reg_write(REG_MODE_1, val);
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/*
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* Set switchers in Auto in NORMAL mode & STANDBY mode
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* Setup the switcher mode for SW1 & SW2
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*/
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val = pmic_reg_read(REG_SW_4);
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val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
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(SWMODE_MASK << SWMODE2_SHIFT)));
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val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
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pmic_reg_write(REG_SW_4, val);
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/* Setup the switcher mode for SW3 & SW4 */
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val = pmic_reg_read(REG_SW_5);
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val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
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(SWMODE_MASK << SWMODE3_SHIFT));
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val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
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(SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
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pmic_reg_write(REG_SW_5, val);
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/* Set VGEN3 to 1.8V, VCAM to 3.0V */
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val = pmic_reg_read(REG_SETTING_0);
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val &= ~(VCAM_MASK | VGEN3_MASK);
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val |= VCAM_3_0;
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pmic_reg_write(REG_SETTING_0, val);
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/* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */
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val = pmic_reg_read(REG_SETTING_1);
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val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
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val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8;
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pmic_reg_write(REG_SETTING_1, val);
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = VGEN3CONFIG | VCAMCONFIG;
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pmic_reg_write(REG_MODE_1, val);
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udelay(200);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
|
|
val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
|
|
VVIDEOEN | VAUDIOEN | VSDEN;
|
|
pmic_reg_write(REG_MODE_1, val);
|
|
|
|
val = pmic_reg_read(REG_POWER_CTL2);
|
|
val |= WDIRESET;
|
|
pmic_reg_write(REG_POWER_CTL2, val);
|
|
|
|
udelay(2500);
|
|
|
|
}
|
|
#endif
|
|
|
|
static void setup_gpios(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
/* CAM_SUP_DISn, GPIO1_7 */
|
|
mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82);
|
|
|
|
/* DAB Display EN, GPIO3_1 */
|
|
mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
|
|
mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82);
|
|
|
|
/* WDOG_TRIGGER, GPIO3_2 */
|
|
mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4);
|
|
mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82);
|
|
|
|
/* Now we need to trigger the watchdog */
|
|
WATCHDOG_RESET();
|
|
|
|
/* Display2 TxEN, GPIO3_3 */
|
|
mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
|
|
mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82);
|
|
|
|
/* DAB Light EN, GPIO3_4 */
|
|
mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
|
|
mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82);
|
|
|
|
/* AUDIO_MUTE, GPIO3_5 */
|
|
mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4);
|
|
mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82);
|
|
|
|
/* SPARE_OUT, GPIO3_6 */
|
|
mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
|
|
mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82);
|
|
|
|
/* BEEPER_EN, GPIO3_26 */
|
|
mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82);
|
|
|
|
/* POWER_OFF, GPIO3_27 */
|
|
mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82);
|
|
|
|
/* FRAM_WE, GPIO3_30 */
|
|
mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82);
|
|
|
|
/* EXPANSION_EN, GPIO4_26 */
|
|
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82);
|
|
|
|
/*
|
|
* Set GPIO1_4 to high and output; it is used to reset
|
|
* the system on reboot
|
|
*/
|
|
mxc_gpio_set(4, 1);
|
|
mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT);
|
|
|
|
mxc_gpio_set(7, 0);
|
|
mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT);
|
|
for (i = 65; i < 71; i++) {
|
|
mxc_gpio_set(i, 0);
|
|
mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT);
|
|
}
|
|
|
|
mxc_gpio_set(94, 0);
|
|
mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT);
|
|
|
|
/* Set POWER_OFF high */
|
|
mxc_gpio_set(91, 1);
|
|
mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT);
|
|
|
|
mxc_gpio_set(90, 0);
|
|
mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT);
|
|
|
|
mxc_gpio_set(122, 0);
|
|
mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT);
|
|
|
|
mxc_gpio_set(121, 1);
|
|
mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT);
|
|
|
|
WATCHDOG_RESET();
|
|
}
|
|
|
|
static void setup_fec(void)
|
|
{
|
|
/*FEC_MDIO*/
|
|
mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD);
|
|
|
|
/*FEC_MDC*/
|
|
mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
|
|
|
|
/* FEC RDATA[3] */
|
|
mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
|
|
|
|
/* FEC RDATA[2] */
|
|
mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
|
|
|
|
/* FEC RDATA[1] */
|
|
mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
|
|
|
|
/* FEC RDATA[0] */
|
|
mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
|
|
|
|
/* FEC TDATA[3] */
|
|
mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
|
|
|
|
/* FEC TDATA[2] */
|
|
mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
|
|
|
|
/* FEC TDATA[1] */
|
|
mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
|
|
|
|
/* FEC TDATA[0] */
|
|
mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
|
|
|
|
/* FEC TX_EN */
|
|
mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
|
|
|
|
/* FEC TX_ER */
|
|
mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
|
|
|
|
/* FEC TX_CLK */
|
|
mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
|
|
|
|
/* FEC TX_COL */
|
|
mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
|
|
|
|
/* FEC RX_CLK */
|
|
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
|
|
|
|
/* FEC RX_CRS */
|
|
mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
|
|
|
|
/* FEC RX_ER */
|
|
mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
|
|
mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
|
|
|
|
/* FEC RX_DV */
|
|
mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
|
|
mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
|
|
}
|
|
|
|
struct fsl_esdhc_cfg esdhc_cfg[1] = {
|
|
{MMC_SDHC1_BASE_ADDR, 1},
|
|
};
|
|
|
|
int get_mmc_getcd(u8 *cd, struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
|
|
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
|
|
*cd = mxc_gpio_get(0);
|
|
else
|
|
*cd = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
mxc_request_iomux(MX51_PIN_SD1_CMD,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_SD1_CLK,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_SD1_DATA0,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_SD1_DATA1,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_SD1_DATA2,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_request_iomux(MX51_PIN_SD1_DATA3,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
|
PAD_CTL_PUE_PULL |
|
|
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
|
PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
|
|
PAD_CTL_PUE_PULL |
|
|
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
|
PAD_CTL_PUE_PULL |
|
|
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
|
PAD_CTL_PUE_PULL |
|
|
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
|
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
|
PAD_CTL_PUE_PULL |
|
|
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
|
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
|
|
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
|
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
|
|
PAD_CTL_PUE_PULL |
|
|
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_0,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
|
|
PAD_CTL_HYS_ENABLE);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_1,
|
|
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
|
|
PAD_CTL_HYS_ENABLE);
|
|
|
|
return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
|
|
}
|
|
#endif
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
|
|
|
|
init_drive_strength();
|
|
|
|
/* Setup debug led */
|
|
mxc_gpio_set(6, 0);
|
|
mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT);
|
|
mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
|
|
mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
|
|
|
|
/* wait a little while to give the pll time to settle */
|
|
sdelay(100000);
|
|
|
|
setup_weim();
|
|
setup_uart();
|
|
setup_fec();
|
|
setup_gpios();
|
|
|
|
spi_io_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
|
|
board_early_init_f();
|
|
#endif
|
|
gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
power_init_mx51();
|
|
|
|
reset_peripherals(1);
|
|
udelay(2000);
|
|
reset_peripherals(0);
|
|
udelay(2000);
|
|
|
|
/* Early revisions require a second reset */
|
|
#ifdef CONFIG_VISION2_HW_1_0
|
|
reset_peripherals(1);
|
|
udelay(2000);
|
|
reset_peripherals(0);
|
|
udelay(2000);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
u32 system_rev = get_cpu_rev();
|
|
u32 cause;
|
|
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
|
|
|
puts("Board: TTControl Vision II CPU V");
|
|
|
|
switch (system_rev & 0xff) {
|
|
case CHIP_REV_3_0:
|
|
puts("3.0 [");
|
|
break;
|
|
case CHIP_REV_2_5:
|
|
puts("2.5 [");
|
|
break;
|
|
case CHIP_REV_2_0:
|
|
puts("2.0 [");
|
|
break;
|
|
case CHIP_REV_1_1:
|
|
puts("1.1 [");
|
|
break;
|
|
case CHIP_REV_1_0:
|
|
default:
|
|
puts("1.0 [");
|
|
break;
|
|
}
|
|
|
|
cause = src_regs->srsr;
|
|
switch (cause) {
|
|
case 0x0001:
|
|
puts("POR");
|
|
break;
|
|
case 0x0009:
|
|
puts("RST");
|
|
break;
|
|
case 0x0010:
|
|
case 0x0011:
|
|
puts("WDOG");
|
|
break;
|
|
default:
|
|
printf("unknown 0x%x", cause);
|
|
}
|
|
puts("]\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
|