upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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108 lines
2.8 KiB
108 lines
2.8 KiB
/*
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* (C) Copyright 2011
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* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
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*
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* (C) Copyright 2015
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* Kamil Lulko, <rev13@wp.pl>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MACH_STM32_H_
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#define _MACH_STM32_H_
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/*
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* Peripheral memory map
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*/
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#define STM32_PERIPH_BASE 0x40000000
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#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
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#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
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#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
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#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000)
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#define STM32_BUS_MASK 0xFFFF0000
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/*
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* Register maps
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*/
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struct stm32_rcc_regs {
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u32 cr; /* RCC clock control */
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u32 pllcfgr; /* RCC PLL configuration */
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u32 cfgr; /* RCC clock configuration */
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u32 cir; /* RCC clock interrupt */
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u32 ahb1rstr; /* RCC AHB1 peripheral reset */
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u32 ahb2rstr; /* RCC AHB2 peripheral reset */
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u32 ahb3rstr; /* RCC AHB3 peripheral reset */
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u32 rsv0;
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u32 apb1rstr; /* RCC APB1 peripheral reset */
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u32 apb2rstr; /* RCC APB2 peripheral reset */
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u32 rsv1[2];
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u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
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u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
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u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
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u32 rsv2;
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u32 apb1enr; /* RCC APB1 peripheral clock enable */
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u32 apb2enr; /* RCC APB2 peripheral clock enable */
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u32 rsv3[2];
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u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
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u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
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u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
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u32 rsv4;
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u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
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u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
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u32 rsv5[2];
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u32 bdcr; /* RCC Backup domain control */
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u32 csr; /* RCC clock control & status */
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u32 rsv6[2];
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u32 sscgr; /* RCC spread spectrum clock generation */
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u32 plli2scfgr; /* RCC PLLI2S configuration */
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u32 pllsaicfgr;
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u32 dckcfgr;
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};
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struct stm32_pwr_regs {
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u32 cr;
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u32 csr;
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};
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struct stm32_flash_regs {
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u32 acr;
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u32 key;
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u32 optkeyr;
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u32 sr;
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u32 cr;
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u32 optcr;
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u32 optcr1;
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};
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/*
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* Registers access macros
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*/
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#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
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#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
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#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000)
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#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE)
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#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
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#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE)
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#define STM32_FLASH_SR_BSY (1 << 16)
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#define STM32_FLASH_CR_PG (1 << 0)
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#define STM32_FLASH_CR_SER (1 << 1)
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#define STM32_FLASH_CR_STRT (1 << 16)
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#define STM32_FLASH_CR_LOCK (1 << 31)
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#define STM32_FLASH_CR_SNB_OFFSET 3
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enum clock {
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CLOCK_CORE,
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CLOCK_AHB,
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CLOCK_APB1,
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CLOCK_APB2
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};
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int configure_clocks(void);
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unsigned long clock_get(enum clock clck);
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#endif /* _MACH_STM32_H_ */
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