upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
1.4 KiB
61 lines
1.4 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/device.h>
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#include <asm/arch/quark.h>
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/*
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* Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
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*
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* We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this
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* pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata()
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* in the Intel ICH6 GPIO driver where it calls PCI configuration space access
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* APIs which will trigger PCI enumeration process.
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*
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* Check <asm/arch-quark/quark.h> for more details.
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*/
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void board_assert_perst(void)
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{
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u32 base, port, val;
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/* retrieve the GPIO IO base */
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qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
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base = (base & 0xffff) & ~0x7f;
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/* enable the pin */
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port = base + 0x20;
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val = inl(port);
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val |= (1 << 0);
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outl(val, port);
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/* configure the pin as output */
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port = base + 0x24;
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val = inl(port);
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val &= ~(1 << 0);
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outl(val, port);
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/* pull it down (assert) */
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port = base + 0x28;
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val = inl(port);
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val &= ~(1 << 0);
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outl(val, port);
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}
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void board_deassert_perst(void)
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{
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u32 base, port, val;
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/* retrieve the GPIO IO base */
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qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
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base = (base & 0xffff) & ~0x7f;
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/* pull it up (de-assert) */
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port = base + 0x28;
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val = inl(port);
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val |= (1 << 0);
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outl(val, port);
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}
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