upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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84 lines
2.0 KiB
84 lines
2.0 KiB
/*
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* Copyright 2013 Stefan Roese <sr@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/imx-common/regs-common.h>
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/* 1 second delay should be plenty of time for block reset. */
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#define RESET_MAX_TIMEOUT 1000000
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#define MXS_BLOCK_SFTRST (1 << 31)
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#define MXS_BLOCK_CLKGATE (1 << 30)
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int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == mask)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == 0)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_reset_block(struct mxs_register_32 *reg)
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{
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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/* Set SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_set);
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/* Wait for CLKGATE being set */
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if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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return 0;
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}
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