upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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534 lines
12 KiB
534 lines
12 KiB
/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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* Rajeshawari Shinde <rajeshwari.s@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <bouncebuf.h>
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#include <common.h>
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#include <errno.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <mmc.h>
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#include <dwmmc.h>
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#define PAGE_SIZE 4096
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static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
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{
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unsigned long timeout = 1000;
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u32 ctrl;
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dwmci_writel(host, DWMCI_CTRL, value);
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while (timeout--) {
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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if (!(ctrl & DWMCI_RESET_ALL))
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return 1;
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}
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return 0;
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}
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static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
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u32 desc0, u32 desc1, u32 desc2)
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{
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struct dwmci_idmac *desc = idmac;
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desc->flags = desc0;
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desc->cnt = desc1;
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desc->addr = desc2;
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desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
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}
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static void dwmci_prepare_data(struct dwmci_host *host,
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struct mmc_data *data,
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struct dwmci_idmac *cur_idmac,
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void *bounce_buffer)
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{
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unsigned long ctrl;
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unsigned int i = 0, flags, cnt, blk_cnt;
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ulong data_start, data_end;
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blk_cnt = data->blocks;
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dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
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data_start = (ulong)cur_idmac;
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dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
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do {
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flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
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flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
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if (blk_cnt <= 8) {
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flags |= DWMCI_IDMAC_LD;
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cnt = data->blocksize * blk_cnt;
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} else
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cnt = data->blocksize * 8;
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dwmci_set_idma_desc(cur_idmac, flags, cnt,
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(ulong)bounce_buffer + (i * PAGE_SIZE));
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if (blk_cnt <= 8)
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break;
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blk_cnt -= 8;
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cur_idmac++;
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i++;
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} while(1);
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data_end = (ulong)cur_idmac;
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flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
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dwmci_writel(host, DWMCI_CTRL, ctrl);
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ctrl = dwmci_readl(host, DWMCI_BMOD);
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ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
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dwmci_writel(host, DWMCI_BMOD, ctrl);
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dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
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dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
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}
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static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
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{
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int ret = 0;
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u32 timeout = 240000;
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u32 mask, size, i, len = 0;
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u32 *buf = NULL;
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ulong start = get_timer(0);
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u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
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RX_WMARK_SHIFT) + 1) * 2;
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size = data->blocksize * data->blocks / 4;
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if (data->flags == MMC_DATA_READ)
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buf = (unsigned int *)data->dest;
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else
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buf = (unsigned int *)data->src;
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for (;;) {
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mask = dwmci_readl(host, DWMCI_RINTSTS);
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/* Error during data transfer. */
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if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
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debug("%s: DATA ERROR!\n", __func__);
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ret = -EINVAL;
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break;
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}
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if (host->fifo_mode && size) {
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len = 0;
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if (data->flags == MMC_DATA_READ &&
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(mask & DWMCI_INTMSK_RXDR)) {
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while (size) {
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len = dwmci_readl(host, DWMCI_STATUS);
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len = (len >> DWMCI_FIFO_SHIFT) &
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DWMCI_FIFO_MASK;
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len = min(size, len);
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for (i = 0; i < len; i++)
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*buf++ =
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dwmci_readl(host, DWMCI_DATA);
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size = size > len ? (size - len) : 0;
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}
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dwmci_writel(host, DWMCI_RINTSTS,
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DWMCI_INTMSK_RXDR);
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} else if (data->flags == MMC_DATA_WRITE &&
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(mask & DWMCI_INTMSK_TXDR)) {
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while (size) {
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len = dwmci_readl(host, DWMCI_STATUS);
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len = fifo_depth - ((len >>
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DWMCI_FIFO_SHIFT) &
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DWMCI_FIFO_MASK);
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len = min(size, len);
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for (i = 0; i < len; i++)
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dwmci_writel(host, DWMCI_DATA,
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*buf++);
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size = size > len ? (size - len) : 0;
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}
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dwmci_writel(host, DWMCI_RINTSTS,
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DWMCI_INTMSK_TXDR);
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}
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}
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/* Data arrived correctly. */
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if (mask & DWMCI_INTMSK_DTO) {
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ret = 0;
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break;
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}
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/* Check for timeout. */
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if (get_timer(start) > timeout) {
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debug("%s: Timeout waiting for data!\n",
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__func__);
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ret = -ETIMEDOUT;
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break;
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}
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}
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dwmci_writel(host, DWMCI_RINTSTS, mask);
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return ret;
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}
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static int dwmci_set_transfer_mode(struct dwmci_host *host,
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struct mmc_data *data)
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{
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unsigned long mode;
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mode = DWMCI_CMD_DATA_EXP;
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if (data->flags & MMC_DATA_WRITE)
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mode |= DWMCI_CMD_RW;
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return mode;
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}
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#ifdef CONFIG_DM_MMC_OPS
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static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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#else
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static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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#endif
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struct dwmci_host *host = mmc->priv;
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ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
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data ? DIV_ROUND_UP(data->blocks, 8) : 0);
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int ret = 0, flags = 0, i;
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unsigned int timeout = 500;
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u32 retry = 100000;
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u32 mask, ctrl;
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ulong start = get_timer(0);
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struct bounce_buffer bbstate;
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while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
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if (get_timer(start) > timeout) {
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debug("%s: Timeout on data busy\n", __func__);
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return -ETIMEDOUT;
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}
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}
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dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
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if (data) {
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if (host->fifo_mode) {
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dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
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dwmci_writel(host, DWMCI_BYTCNT,
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data->blocksize * data->blocks);
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dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
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} else {
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if (data->flags == MMC_DATA_READ) {
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bounce_buffer_start(&bbstate, (void*)data->dest,
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data->blocksize *
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data->blocks, GEN_BB_WRITE);
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} else {
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bounce_buffer_start(&bbstate, (void*)data->src,
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data->blocksize *
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data->blocks, GEN_BB_READ);
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}
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dwmci_prepare_data(host, data, cur_idmac,
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bbstate.bounce_buffer);
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}
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}
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dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
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if (data)
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flags = dwmci_set_transfer_mode(host, data);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -1;
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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flags |= DWMCI_CMD_ABORT_STOP;
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else
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flags |= DWMCI_CMD_PRV_DAT_WAIT;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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flags |= DWMCI_CMD_RESP_EXP;
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if (cmd->resp_type & MMC_RSP_136)
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flags |= DWMCI_CMD_RESP_LENGTH;
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}
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= DWMCI_CMD_CHECK_CRC;
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flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
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debug("Sending CMD%d\n",cmd->cmdidx);
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dwmci_writel(host, DWMCI_CMD, flags);
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for (i = 0; i < retry; i++) {
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mask = dwmci_readl(host, DWMCI_RINTSTS);
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if (mask & DWMCI_INTMSK_CDONE) {
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if (!data)
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dwmci_writel(host, DWMCI_RINTSTS, mask);
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break;
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}
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}
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if (i == retry) {
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debug("%s: Timeout.\n", __func__);
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return -ETIMEDOUT;
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}
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if (mask & DWMCI_INTMSK_RTO) {
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/*
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* Timeout here is not necessarily fatal. (e)MMC cards
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* will splat here when they receive CMD55 as they do
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* not support this command and that is exactly the way
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* to tell them apart from SD cards. Thus, this output
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* below shall be debug(). eMMC cards also do not favor
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* CMD8, please keep that in mind.
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*/
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debug("%s: Response Timeout.\n", __func__);
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return -ETIMEDOUT;
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} else if (mask & DWMCI_INTMSK_RE) {
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debug("%s: Response Error.\n", __func__);
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return -EIO;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
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cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
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cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
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cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
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} else {
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
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}
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}
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if (data) {
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ret = dwmci_data_transfer(host, data);
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/* only dma mode need it */
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if (!host->fifo_mode) {
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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ctrl &= ~(DWMCI_DMA_EN);
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dwmci_writel(host, DWMCI_CTRL, ctrl);
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bounce_buffer_stop(&bbstate);
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}
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}
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udelay(100);
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return ret;
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}
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static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
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{
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u32 div, status;
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int timeout = 10000;
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unsigned long sclk;
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if ((freq == host->clock) || (freq == 0))
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return 0;
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/*
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* If host->get_mmc_clk isn't defined,
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* then assume that host->bus_hz is source clock value.
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* host->bus_hz should be set by user.
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*/
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if (host->get_mmc_clk)
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sclk = host->get_mmc_clk(host, freq);
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else if (host->bus_hz)
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sclk = host->bus_hz;
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else {
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debug("%s: Didn't get source clock value.\n", __func__);
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return -EINVAL;
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}
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if (sclk == freq)
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div = 0; /* bypass mode */
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else
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div = DIV_ROUND_UP(sclk, 2 * freq);
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dwmci_writel(host, DWMCI_CLKENA, 0);
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dwmci_writel(host, DWMCI_CLKSRC, 0);
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dwmci_writel(host, DWMCI_CLKDIV, div);
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dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
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DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
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do {
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status = dwmci_readl(host, DWMCI_CMD);
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if (timeout-- < 0) {
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debug("%s: Timeout!\n", __func__);
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return -ETIMEDOUT;
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}
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} while (status & DWMCI_CMD_START);
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dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
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DWMCI_CLKEN_LOW_PWR);
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dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
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DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
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timeout = 10000;
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do {
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status = dwmci_readl(host, DWMCI_CMD);
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if (timeout-- < 0) {
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debug("%s: Timeout!\n", __func__);
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return -ETIMEDOUT;
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}
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} while (status & DWMCI_CMD_START);
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host->clock = freq;
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return 0;
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}
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#ifdef CONFIG_DM_MMC_OPS
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static int dwmci_set_ios(struct udevice *dev)
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{
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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#else
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static void dwmci_set_ios(struct mmc *mmc)
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{
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#endif
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
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u32 ctype, regs;
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debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
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dwmci_setup_bus(host, mmc->clock);
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switch (mmc->bus_width) {
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case 8:
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ctype = DWMCI_CTYPE_8BIT;
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break;
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case 4:
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ctype = DWMCI_CTYPE_4BIT;
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break;
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default:
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ctype = DWMCI_CTYPE_1BIT;
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break;
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}
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dwmci_writel(host, DWMCI_CTYPE, ctype);
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regs = dwmci_readl(host, DWMCI_UHS_REG);
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if (mmc->ddr_mode)
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regs |= DWMCI_DDR_MODE;
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else
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regs &= ~DWMCI_DDR_MODE;
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dwmci_writel(host, DWMCI_UHS_REG, regs);
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if (host->clksel)
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host->clksel(host);
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#ifdef CONFIG_DM_MMC_OPS
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return 0;
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#endif
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}
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static int dwmci_init(struct mmc *mmc)
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{
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struct dwmci_host *host = mmc->priv;
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if (host->board_init)
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host->board_init(host);
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dwmci_writel(host, DWMCI_PWREN, 1);
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if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
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debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
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return -EIO;
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}
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/* Enumerate at 400KHz */
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dwmci_setup_bus(host, mmc->cfg->f_min);
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dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
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dwmci_writel(host, DWMCI_INTMASK, 0);
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dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
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dwmci_writel(host, DWMCI_IDINTEN, 0);
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dwmci_writel(host, DWMCI_BMOD, 1);
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if (!host->fifoth_val) {
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uint32_t fifo_size;
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fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
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fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
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host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
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TX_WMARK(fifo_size / 2);
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}
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dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
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dwmci_writel(host, DWMCI_CLKENA, 0);
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dwmci_writel(host, DWMCI_CLKSRC, 0);
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return 0;
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}
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#ifdef CONFIG_DM_MMC_OPS
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int dwmci_probe(struct udevice *dev)
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{
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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return dwmci_init(mmc);
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}
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const struct dm_mmc_ops dm_dwmci_ops = {
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.send_cmd = dwmci_send_cmd,
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.set_ios = dwmci_set_ios,
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};
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#else
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static const struct mmc_ops dwmci_ops = {
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.send_cmd = dwmci_send_cmd,
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.set_ios = dwmci_set_ios,
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.init = dwmci_init,
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};
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#endif
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void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
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uint caps, u32 max_clk, u32 min_clk)
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{
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cfg->name = name;
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#ifndef CONFIG_DM_MMC_OPS
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cfg->ops = &dwmci_ops;
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#endif
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cfg->f_min = min_clk;
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cfg->f_max = max_clk;
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|
|
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cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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|
|
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cfg->host_caps = caps;
|
|
|
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if (buswidth == 8) {
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cfg->host_caps |= MMC_MODE_8BIT;
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cfg->host_caps &= ~MMC_MODE_4BIT;
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} else {
|
|
cfg->host_caps |= MMC_MODE_4BIT;
|
|
cfg->host_caps &= ~MMC_MODE_8BIT;
|
|
}
|
|
cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
|
|
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
}
|
|
|
|
#ifdef CONFIG_BLK
|
|
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
|
|
{
|
|
return mmc_bind(dev, mmc, cfg);
|
|
}
|
|
#else
|
|
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
|
|
{
|
|
dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
|
|
max_clk, min_clk);
|
|
|
|
host->mmc = mmc_create(&host->cfg, host);
|
|
if (host->mmc == NULL)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|