upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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439 lines
11 KiB
439 lines
11 KiB
/*
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* Marvell MMC/SD/SDIO driver
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*
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* (C) Copyright 2012-2014
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Maen Suleiman, Gerald Kerma
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <malloc.h>
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#include <part.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <mvebu_mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define DRIVER_NAME "MVEBU_MMC"
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#define MVEBU_TARGET_DRAM 0
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#define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
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static void mvebu_mmc_write(u32 offs, u32 val)
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{
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writel(val, CONFIG_SYS_MMC_BASE + (offs));
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}
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static u32 mvebu_mmc_read(u32 offs)
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{
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return readl(CONFIG_SYS_MMC_BASE + (offs));
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}
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static int mvebu_mmc_setup_data(struct mmc_data *data)
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{
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u32 ctrl_reg;
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debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
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(data->flags & MMC_DATA_READ) ? "read" : "write",
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data->blocks, data->blocksize);
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/* default to maximum timeout */
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ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
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ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
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mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
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if (data->flags & MMC_DATA_READ) {
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mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
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mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
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} else {
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mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
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mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
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}
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mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
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mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
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return 0;
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}
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static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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ulong start;
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ushort waittype = 0;
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ushort resptype = 0;
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ushort xfertype = 0;
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ushort resp_indx = 0;
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debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
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DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
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debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
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cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
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/*
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* Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
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* register is sometimes not set before a while when some
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* "unusual" data block sizes are used (such as with the SWITCH
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* command), even despite the fact that the XFER_DONE interrupt
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* was raised. And if another data transfer starts before
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* this bit comes to good sense (which eventually happens by
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* itself) then the new transfer simply fails with a timeout.
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*/
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if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
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ushort hw_state, count = 0;
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start = get_timer(0);
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do {
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hw_state = mvebu_mmc_read(SDIO_HW_STATE);
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if ((get_timer(0) - start) > TIMEOUT_DELAY) {
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printf("%s : FIFO_EMPTY bit missing\n",
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DRIVER_NAME);
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break;
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}
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count++;
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} while (!(hw_state & CMD_FIFO_EMPTY));
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debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
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DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
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}
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/* Clear status */
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mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
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mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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resptype = SDIO_CMD_INDEX(cmd->cmdidx);
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/* Analyzing resptype/xfertype/waittype for the command */
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if (cmd->resp_type & MMC_RSP_BUSY)
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resptype |= SDIO_CMD_RSP_48BUSY;
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else if (cmd->resp_type & MMC_RSP_136)
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resptype |= SDIO_CMD_RSP_136;
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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resptype |= SDIO_CMD_RSP_48;
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else
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resptype |= SDIO_CMD_RSP_NONE;
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if (cmd->resp_type & MMC_RSP_CRC)
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resptype |= SDIO_CMD_CHECK_CMDCRC;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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resptype |= SDIO_CMD_INDX_CHECK;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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resptype |= SDIO_UNEXPECTED_RESP;
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waittype |= SDIO_NOR_UNEXP_RSP;
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}
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if (data) {
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int err = mvebu_mmc_setup_data(data);
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if (err) {
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debug("%s: command DATA error :%x\n",
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DRIVER_NAME, err);
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return err;
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}
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resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
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xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
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if (data->flags & MMC_DATA_READ) {
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xfertype |= SDIO_XFER_MODE_TO_HOST;
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waittype = SDIO_NOR_DMA_INI;
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} else {
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waittype |= SDIO_NOR_XFER_DONE;
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}
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} else {
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waittype |= SDIO_NOR_CMD_DONE;
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}
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/* Setting cmd arguments */
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mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
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mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
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/* Setting Xfer mode */
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mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
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/* Sending command */
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mvebu_mmc_write(SDIO_CMD, resptype);
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start = get_timer(0);
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while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
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if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
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debug("%s: error! cmdidx : %d, err reg: %04x\n",
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DRIVER_NAME, cmd->cmdidx,
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mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
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if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
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debug("%s: command READ timed out\n",
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DRIVER_NAME);
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return -ETIMEDOUT;
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}
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debug("%s: command READ error\n", DRIVER_NAME);
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return -ECOMM;
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}
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if ((get_timer(0) - start) > TIMEOUT_DELAY) {
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debug("%s: command timed out\n", DRIVER_NAME);
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return -ETIMEDOUT;
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}
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}
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/* Handling response */
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if (cmd->resp_type & MMC_RSP_136) {
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uint response[8];
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for (resp_indx = 0; resp_indx < 8; resp_indx++)
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response[resp_indx]
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= mvebu_mmc_read(SDIO_RSP(resp_indx));
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cmd->response[0] = ((response[0] & 0x03ff) << 22) |
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((response[1] & 0xffff) << 6) |
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((response[2] & 0xfc00) >> 10);
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cmd->response[1] = ((response[2] & 0x03ff) << 22) |
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((response[3] & 0xffff) << 6) |
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((response[4] & 0xfc00) >> 10);
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cmd->response[2] = ((response[4] & 0x03ff) << 22) |
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((response[5] & 0xffff) << 6) |
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((response[6] & 0xfc00) >> 10);
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cmd->response[3] = ((response[6] & 0x03ff) << 22) |
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((response[7] & 0x3fff) << 8);
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} else if (cmd->resp_type & MMC_RSP_PRESENT) {
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uint response[3];
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for (resp_indx = 0; resp_indx < 3; resp_indx++)
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response[resp_indx]
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= mvebu_mmc_read(SDIO_RSP(resp_indx));
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cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
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((response[1] & 0xffff) << (14 - 8)) |
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((response[0] & 0x03ff) << (30 - 8));
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cmd->response[1] = ((response[0] & 0xfc00) >> 10);
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cmd->response[2] = 0;
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cmd->response[3] = 0;
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} else {
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cmd->response[0] = 0;
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cmd->response[1] = 0;
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cmd->response[2] = 0;
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cmd->response[3] = 0;
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}
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debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
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debug("[0x%x] ", cmd->response[0]);
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debug("[0x%x] ", cmd->response[1]);
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debug("[0x%x] ", cmd->response[2]);
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debug("[0x%x] ", cmd->response[3]);
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debug("\n");
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if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
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return -ETIMEDOUT;
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return 0;
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}
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static void mvebu_mmc_power_up(void)
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{
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debug("%s: power up\n", DRIVER_NAME);
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/* disable interrupts */
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mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
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mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
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/* SW reset */
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mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
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mvebu_mmc_write(SDIO_XFER_MODE, 0);
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/* enable status */
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mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
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mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
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/* enable interrupts status */
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mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
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mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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}
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static void mvebu_mmc_set_clk(unsigned int clock)
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{
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unsigned int m;
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if (clock == 0) {
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debug("%s: clock off\n", DRIVER_NAME);
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mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
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mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
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} else {
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m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
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if (m > MVEBU_MMC_BASE_DIV_MAX)
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m = MVEBU_MMC_BASE_DIV_MAX;
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mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
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debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
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}
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}
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static void mvebu_mmc_set_bus(unsigned int bus)
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{
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u32 ctrl_reg = 0;
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ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
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ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
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switch (bus) {
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case 4:
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ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
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break;
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case 1:
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default:
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ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
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}
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/* default transfer mode */
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ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
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ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
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/* default to maximum timeout */
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ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
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ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
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ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
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ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
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debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
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(ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
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"push-pull" : "open-drain",
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(ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
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"4bit-width" : "1bit-width",
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(ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
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"high-speed" : "");
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mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
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}
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static void mvebu_mmc_set_ios(struct mmc *mmc)
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{
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debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
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mmc->bus_width, mmc->clock);
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mvebu_mmc_set_bus(mmc->bus_width);
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mvebu_mmc_set_clk(mmc->clock);
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}
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/*
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* Set window register.
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*/
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static void mvebu_window_setup(void)
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{
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int i;
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for (i = 0; i < 4; i++) {
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mvebu_mmc_write(WINDOW_CTRL(i), 0);
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mvebu_mmc_write(WINDOW_BASE(i), 0);
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}
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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u32 size, base, attrib;
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/* Enable DRAM bank */
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switch (i) {
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case 0:
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attrib = KWCPU_ATTR_DRAM_CS0;
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break;
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case 1:
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attrib = KWCPU_ATTR_DRAM_CS1;
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break;
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case 2:
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attrib = KWCPU_ATTR_DRAM_CS2;
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break;
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case 3:
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attrib = KWCPU_ATTR_DRAM_CS3;
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break;
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default:
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/* invalide bank, disable access */
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attrib = 0;
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break;
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}
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size = gd->bd->bi_dram[i].size;
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base = gd->bd->bi_dram[i].start;
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if (size && attrib) {
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mvebu_mmc_write(WINDOW_CTRL(i),
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MVCPU_WIN_CTRL_DATA(size,
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MVEBU_TARGET_DRAM,
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attrib,
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MVCPU_WIN_ENABLE));
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} else {
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mvebu_mmc_write(WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
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}
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mvebu_mmc_write(WINDOW_BASE(i), base);
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}
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}
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static int mvebu_mmc_initialize(struct mmc *mmc)
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{
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debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
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/*
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* Setting host parameters
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* Initial Host Ctrl : Timeout : max , Normal Speed mode,
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* 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
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*/
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mvebu_mmc_write(SDIO_HOST_CTRL,
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SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
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SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
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SDIO_HOST_CTRL_BIG_ENDIAN |
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SDIO_HOST_CTRL_PUSH_PULL_EN |
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SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
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mvebu_mmc_write(SDIO_CLK_CTRL, 0);
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/* enable status */
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mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
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mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
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/* disable interrupts */
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mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
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mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
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mvebu_window_setup();
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/* SW reset */
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mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
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return 0;
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}
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static const struct mmc_ops mvebu_mmc_ops = {
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.send_cmd = mvebu_mmc_send_cmd,
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.set_ios = mvebu_mmc_set_ios,
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.init = mvebu_mmc_initialize,
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};
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static struct mmc_config mvebu_mmc_cfg = {
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.name = DRIVER_NAME,
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.ops = &mvebu_mmc_ops,
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.f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
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.f_max = MVEBU_MMC_CLOCKRATE_MAX,
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.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
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.host_caps = MMC_MODE_4BIT | MMC_MODE_HS |
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MMC_MODE_HS_52MHz,
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.part_type = PART_TYPE_DOS,
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.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
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};
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int mvebu_mmc_init(bd_t *bis)
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{
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struct mmc *mmc;
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mvebu_mmc_power_up();
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mmc = mmc_create(&mvebu_mmc_cfg, bis);
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if (mmc == NULL)
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return -1;
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return 0;
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}
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