upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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24 lines
722 B
24 lines
722 B
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*/
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#ifndef __SANDBOX_CACHE_H__
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#define __SANDBOX_CACHE_H__
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/*
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* For native compilation of the sandbox we should still align
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* the contents of stack buffers to something reasonable. The
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* GCC macro __BIGGEST_ALIGNMENT__ is defined to be the maximum
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* required alignment for any basic type. This seems reasonable.
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* This is however GCC specific so if we don't have that available
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* assume that 16 is large enough.
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*/
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#ifdef __BIGGEST_ALIGNMENT__
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#define ARCH_DMA_MINALIGN __BIGGEST_ALIGNMENT__
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#else
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#define ARCH_DMA_MINALIGN 16
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#endif
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#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
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#endif /* __SANDBOX_CACHE_H__ */
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