upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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438 lines
9.1 KiB
438 lines
9.1 KiB
/*
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* i2c driver for Freescale i.MX series
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2011 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on i2c-imx.c from linux kernel:
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* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
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* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
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* Copyright (C) 2007 RightHand Technologies, Inc.
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#if defined(CONFIG_HARD_I2C)
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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struct mxc_i2c_regs {
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uint32_t iadr;
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uint32_t ifdr;
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uint32_t i2cr;
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uint32_t i2sr;
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uint32_t i2dr;
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};
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#define I2CR_IEN (1 << 7)
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#define I2CR_IIEN (1 << 6)
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#define I2CR_MSTA (1 << 5)
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#define I2CR_MTX (1 << 4)
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#define I2CR_TX_NO_AK (1 << 3)
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#define I2CR_RSTA (1 << 2)
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#define I2SR_ICF (1 << 7)
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#define I2SR_IBB (1 << 5)
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#define I2SR_IIF (1 << 1)
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#define I2SR_RX_NO_AK (1 << 0)
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#if defined(CONFIG_SYS_I2C_MX31_PORT1)
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#define I2C_BASE 0x43f80000
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#define I2C_CLK_OFFSET 26
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#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
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#define I2C_BASE 0x43f98000
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#define I2C_CLK_OFFSET 28
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#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
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#define I2C_BASE 0x43f84000
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#define I2C_CLK_OFFSET 30
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#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
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#define I2C_BASE I2C1_BASE_ADDR
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#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
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#define I2C_BASE I2C2_BASE_ADDR
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#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
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#define I2C_BASE I2C_BASE_ADDR
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#else
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#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
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#endif
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#define I2C_MAX_TIMEOUT 10000
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static u16 i2c_clk_div[50][2] = {
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
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{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
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{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
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{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
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{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
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{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
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{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
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{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
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{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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static u8 clk_idx;
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/*
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* Calculate and set proper clock divider
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*/
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static void i2c_imx_set_clk(unsigned int rate)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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unsigned int i2c_clk_rate;
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unsigned int div;
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int i;
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#if defined(CONFIG_MX31)
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struct clock_control_regs *sc_regs =
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(struct clock_control_regs *)CCM_BASE;
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/* start the required I2C clock */
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writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
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&sc_regs->cgr0);
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#endif
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/* Divider value calculation */
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i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
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div = (i2c_clk_rate + rate - 1) / rate;
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if (div < i2c_clk_div[0][0])
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i = 0;
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else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
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i = ARRAY_SIZE(i2c_clk_div) - 1;
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else
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for (i = 0; i2c_clk_div[i][0] < div; i++)
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;
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/* Store divider value */
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clk_idx = i2c_clk_div[i][1];
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writeb(clk_idx, &i2c_regs->ifdr);
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}
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/*
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* Reset I2C Controller
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*/
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void i2c_reset(void)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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writeb(0, &i2c_regs->i2cr); /* Reset module */
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writeb(0, &i2c_regs->i2sr);
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}
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/*
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* Init I2C Bus
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*/
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void i2c_init(int speed, int unused)
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{
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i2c_imx_set_clk(speed);
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i2c_reset();
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}
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/*
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* Wait for bus to be busy (or free if for_busy = 0)
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*
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* for_busy = 1: Wait for IBB to be asserted
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* for_busy = 0: Wait for IBB to be de-asserted
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*/
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int i2c_imx_bus_busy(int for_busy)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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unsigned int temp;
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int timeout = I2C_MAX_TIMEOUT;
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while (timeout--) {
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temp = readb(&i2c_regs->i2sr);
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if (for_busy && (temp & I2SR_IBB))
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return 0;
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if (!for_busy && !(temp & I2SR_IBB))
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return 0;
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udelay(1);
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}
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return 1;
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}
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/*
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* Wait for transaction to complete
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*/
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int i2c_imx_trx_complete(void)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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int timeout = I2C_MAX_TIMEOUT;
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while (timeout--) {
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if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
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writeb(0, &i2c_regs->i2sr);
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return 0;
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}
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udelay(1);
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}
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return 1;
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}
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/*
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* Check if the transaction was ACKed
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*/
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int i2c_imx_acked(void)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
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}
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/*
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* Start the controller
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*/
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int i2c_imx_start(void)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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unsigned int temp = 0;
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int result;
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writeb(clk_idx, &i2c_regs->ifdr);
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/* Enable I2C controller */
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writeb(0, &i2c_regs->i2sr);
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writeb(I2CR_IEN, &i2c_regs->i2cr);
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/* Wait controller to be stable */
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udelay(50);
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/* Start I2C transaction */
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temp = readb(&i2c_regs->i2cr);
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temp |= I2CR_MSTA;
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writeb(temp, &i2c_regs->i2cr);
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result = i2c_imx_bus_busy(1);
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if (result)
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return result;
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temp |= I2CR_MTX | I2CR_TX_NO_AK;
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writeb(temp, &i2c_regs->i2cr);
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return 0;
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}
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/*
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* Stop the controller
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*/
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void i2c_imx_stop(void)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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unsigned int temp = 0;
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/* Stop I2C transaction */
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temp = readb(&i2c_regs->i2cr);
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temp |= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, &i2c_regs->i2cr);
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i2c_imx_bus_busy(0);
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/* Disable I2C controller */
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writeb(0, &i2c_regs->i2cr);
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}
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/*
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* Set chip address and access mode
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*
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* read = 1: READ access
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* read = 0: WRITE access
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*/
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int i2c_imx_set_chip_addr(uchar chip, int read)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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int ret;
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writeb((chip << 1) | read, &i2c_regs->i2dr);
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ret = i2c_imx_trx_complete();
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if (ret)
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return ret;
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ret = i2c_imx_acked();
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if (ret)
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return ret;
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return ret;
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}
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/*
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* Write register address
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*/
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int i2c_imx_set_reg_addr(uint addr, int alen)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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int ret;
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int i;
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for (i = 0; i < (8 * alen); i += 8) {
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writeb((addr >> i) & 0xff, &i2c_regs->i2dr);
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ret = i2c_imx_trx_complete();
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if (ret)
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break;
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ret = i2c_imx_acked();
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if (ret)
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break;
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}
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return ret;
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}
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/*
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* Try if a chip add given address responds (probe the chip)
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*/
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int i2c_probe(uchar chip)
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{
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int ret;
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ret = i2c_imx_start();
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if (ret)
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return ret;
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ret = i2c_imx_set_chip_addr(chip, 0);
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if (ret)
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return ret;
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i2c_imx_stop();
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return ret;
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}
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/*
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* Read data from I2C device
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*/
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int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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int ret;
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unsigned int temp;
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int i;
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ret = i2c_imx_start();
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if (ret)
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return ret;
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/* write slave address */
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ret = i2c_imx_set_chip_addr(chip, 0);
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if (ret)
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return ret;
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ret = i2c_imx_set_reg_addr(addr, alen);
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if (ret)
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return ret;
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temp = readb(&i2c_regs->i2cr);
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temp |= I2CR_RSTA;
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writeb(temp, &i2c_regs->i2cr);
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ret = i2c_imx_set_chip_addr(chip, 1);
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if (ret)
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return ret;
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/* setup bus to read data */
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temp = readb(&i2c_regs->i2cr);
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temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
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if (len == 1)
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temp |= I2CR_TX_NO_AK;
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writeb(temp, &i2c_regs->i2cr);
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readb(&i2c_regs->i2dr);
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/* read data */
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for (i = 0; i < len; i++) {
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ret = i2c_imx_trx_complete();
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if (ret)
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return ret;
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/*
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* It must generate STOP before read I2DR to prevent
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* controller from generating another clock cycle
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*/
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if (i == (len - 1)) {
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temp = readb(&i2c_regs->i2cr);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, &i2c_regs->i2cr);
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i2c_imx_bus_busy(0);
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} else if (i == (len - 2)) {
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temp = readb(&i2c_regs->i2cr);
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temp |= I2CR_TX_NO_AK;
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writeb(temp, &i2c_regs->i2cr);
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}
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buf[i] = readb(&i2c_regs->i2dr);
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}
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i2c_imx_stop();
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return ret;
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}
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/*
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* Write data to I2C device
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*/
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int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
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int ret;
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int i;
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ret = i2c_imx_start();
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if (ret)
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return ret;
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/* write slave address */
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ret = i2c_imx_set_chip_addr(chip, 0);
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if (ret)
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return ret;
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ret = i2c_imx_set_reg_addr(addr, alen);
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if (ret)
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return ret;
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for (i = 0; i < len; i++) {
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writeb(buf[i], &i2c_regs->i2dr);
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ret = i2c_imx_trx_complete();
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if (ret)
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return ret;
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ret = i2c_imx_acked();
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if (ret)
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return ret;
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}
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i2c_imx_stop();
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return ret;
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}
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#endif /* CONFIG_HARD_I2C */
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