upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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166 lines
4.9 KiB
166 lines
4.9 KiB
/*
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* Dave Ethernet Controller driver
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*
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* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DRIVERS_DNET_H__
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#define __DRIVERS_DNET_H__
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#define DRIVERNAME "dnet"
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struct dnet_registers {
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/* ALL DNET FIFO REGISTERS */
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u32 RX_LEN_FIFO;
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u32 RX_DATA_FIFO;
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u32 TX_LEN_FIFO;
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u32 TX_DATA_FIFO;
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u32 pad1[0x3c];
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/* ALL DNET CONTROL/STATUS REGISTERS */
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u32 VERCAPS;
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u32 INTR_SRC;
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u32 INTR_ENB;
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u32 RX_STATUS;
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u32 TX_STATUS;
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u32 RX_FRAMES_CNT;
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u32 TX_FRAMES_CNT;
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u32 RX_FIFO_TH;
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u32 TX_FIFO_TH;
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u32 SYS_CTL;
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u32 PAUSE_TMR;
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u32 RX_FIFO_WCNT;
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u32 TX_FIFO_WCNT;
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u32 pad2[0x33];
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/* ALL DNET MAC REGISTERS */
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u32 MACREG_DATA; /* Mac-Reg Data */
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u32 MACREG_ADDR; /* Mac-Reg Addr */
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u32 pad3[0x3e];
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/* ALL DNET RX STATISTICS COUNTERS */
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u32 RX_PKT_IGNR_CNT;
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u32 RX_LEN_CHK_ERR_CNT;
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u32 RX_LNG_FRM_CNT;
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u32 RX_SHRT_FRM_CNT;
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u32 RX_IPG_VIOL_CNT;
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u32 RX_CRC_ERR_CNT;
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u32 RX_OK_PKT_CNT;
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u32 RX_CTL_FRM_CNT;
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u32 RX_PAUSE_FRM_CNT;
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u32 RX_MULTICAST_CNT;
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u32 RX_BROADCAST_CNT;
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u32 RX_VLAN_TAG_CNT;
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u32 RX_PRE_SHRINK_CNT;
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u32 RX_DRIB_NIB_CNT;
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u32 RX_UNSUP_OPCD_CNT;
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u32 RX_BYTE_CNT;
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u32 pad4[0x30];
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/* DNET TX STATISTICS COUNTERS */
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u32 TX_UNICAST_CNT;
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u32 TX_PAUSE_FRM_CNT;
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u32 TX_MULTICAST_CNT;
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u32 TX_BRDCAST_CNT;
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u32 TX_VLAN_TAG_CNT;
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u32 TX_BAD_FCS_CNT;
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u32 TX_JUMBO_CNT;
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u32 TX_BYTE_CNT;
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};
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/* SOME INTERNAL MAC-CORE REGISTER */
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#define DNET_INTERNAL_MODE_REG 0x0
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#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
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#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
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#define DNET_INTERNAL_IGP_REG 0x8
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#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
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#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
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#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
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#define DNET_INTERNAL_TX_RX_STS_REG 0x12
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#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
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#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
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#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
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#define DNET_INTERNAL_WRITE (1 << 31)
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/* MAC-CORE REGISTER FIELDS */
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/* MAC-CORE MODE REGISTER FIELDS */
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#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
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#define DNET_INTERNAL_MODE_FCEN (1 << 1)
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#define DNET_INTERNAL_MODE_RXEN (1 << 2)
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#define DNET_INTERNAL_MODE_TXEN (1 << 3)
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/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
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#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
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#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
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#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
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#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
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#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
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#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
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#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
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#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
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#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
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/* SYSTEM CONTROL REGISTER FIELDS */
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#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
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#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
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#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
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#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
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/* TX STATUS REGISTER FIELDS */
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#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
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#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
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/* INTERRUPT SOURCE REGISTER FIELDS */
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#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
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#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
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#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
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#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
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#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
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#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
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#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
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#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
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#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
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#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
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#define DNET_INTR_SRC_PHY (1 << 19)
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/* INTERRUPT ENABLE REGISTER FIELDS */
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#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
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#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
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#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
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#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
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#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
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#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
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#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
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#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
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#define DNET_INTR_ENB_RX_ERROR (1 << 11)
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#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
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#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
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#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
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#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
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#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
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/*
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* Capabilities. Used by the driver to know the capabilities that
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* the ethernet controller inside the FPGA have.
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*/
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#define DNET_HAS_MDIO (1 << 0)
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#define DNET_HAS_IRQ (1 << 1)
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#define DNET_HAS_GIGABIT (1 << 2)
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#define DNET_HAS_DMA (1 << 3)
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#define DNET_HAS_MII (1 << 4) /* or GMII */
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#define DNET_HAS_RMII (1 << 5) /* or RGMII */
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#define DNET_CAPS_MASK 0xFFFF
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#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */
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#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
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#define DNET_FIFO_TX_DATA_AE_TH (384)
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#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
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#endif
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