upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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152 lines
5.2 KiB
152 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_dcu_fb.h>
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#include <i2c.h>
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#include <linux/fb.h>
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#define PIXEL_CLK_LSB_REG 0x00
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#define PIXEL_CLK_MSB_REG 0x01
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#define VERT_FREQ_LSB_REG 0x02
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#define VERT_FREQ_MSB_REG 0x03
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#define TOTAL_PIXELS_LSB_REG 0x04
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#define TOTAL_PIXELS_MSB_REG 0x05
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#define TOTAL_LINES_LSB_REG 0x06
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#define TOTAL_LINES_MSB_REG 0x07
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#define TPI_INBUS_FMT_REG 0x08
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#define TPI_INPUT_FMT_REG 0x09
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#define TPI_OUTPUT_FMT_REG 0x0A
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#define TPI_SYS_CTRL_REG 0x1A
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#define TPI_PWR_STAT_REG 0x1E
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#define TPI_AUDIO_HANDING_REG 0x25
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#define TPI_AUDIO_INTF_REG 0x26
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#define TPI_AUDIO_FREQ_REG 0x27
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#define TPI_SET_PAGE_REG 0xBC
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#define TPI_SET_OFFSET_REG 0xBD
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#define TPI_RW_ACCESS_REG 0xBE
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#define TPI_TRANS_MODE_REG 0xC7
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#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6)
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#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5)
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#define TPI_INBUS_RISING_EDGE (1 << 4)
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#define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6)
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#define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2)
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#define TPI_INPUT_CLR_RGB (0 << 0)
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#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 << 6)
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#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 << 2)
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#define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0)
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#define TPI_SYS_TMDS_OUTPUT (0 << 4)
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#define TPI_SYS_AV_NORAML (0 << 3)
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#define TPI_SYS_AV_MUTE (1 << 3)
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#define TPI_SYS_DVI_MODE (0 << 0)
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#define TPI_SYS_HDMI_MODE (1 << 0)
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#define TPI_PWR_STAT_MASK (3 << 0)
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#define TPI_PWR_STAT_D0 (0 << 0)
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#define TPI_AUDIO_PASS_BASIC (0 << 0)
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#define TPI_AUDIO_INTF_I2S (2 << 6)
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#define TPI_AUDIO_INTF_NORMAL (0 << 4)
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#define TPI_AUDIO_TYPE_PCM (1 << 0)
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#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6)
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#define TPI_AUDIO_SAMP_FREQ_44K (2 << 3)
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#define TPI_SET_PAGE_SII9022A 0x01
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#define TPI_SET_OFFSET_SII9022A 0x82
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#define TPI_RW_EN_SRC_TERMIN (1 << 0)
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#define TPI_TRANS_MODE_ENABLE (0 << 7)
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/* Programming of Silicon SIi9022a HDMI Transmitter */
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int dcu_set_dvi_encoder(struct fb_videomode *videomode)
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{
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u8 temp;
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u16 temp1, temp2;
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u32 temp3;
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i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
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/* Enable TPI transmitter mode */
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temp = TPI_TRANS_MODE_ENABLE;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1);
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/* Enter into D0 state, full operation */
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i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
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temp &= ~TPI_PWR_STAT_MASK;
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temp |= TPI_PWR_STAT_D0;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
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/* Enable source termination */
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temp = TPI_SET_PAGE_SII9022A;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1);
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temp = TPI_SET_OFFSET_SII9022A;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1);
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i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
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temp |= TPI_RW_EN_SRC_TERMIN;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
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/* Set TPI system control */
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temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1);
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/* Set pixel clock */
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temp1 = PICOS2KHZ(videomode->pixclock) / 10;
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temp = (u8)(temp1 & 0xFF);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1);
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temp = (u8)(temp1 >> 8);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1);
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/* Set total pixels per line */
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temp1 = videomode->hsync_len + videomode->left_margin +
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videomode->xres + videomode->right_margin;
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temp = (u8)(temp1 & 0xFF);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1);
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temp = (u8)(temp1 >> 8);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1);
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/* Set total lines */
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temp2 = videomode->vsync_len + videomode->upper_margin +
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videomode->yres + videomode->lower_margin;
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temp = (u8)(temp2 & 0xFF);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1);
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temp = (u8)(temp2 >> 8);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1);
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/* Set vertical frequency in Hz */
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temp3 = temp1 * temp2;
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temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
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temp1 = (u16)temp3 * 100;
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temp = (u8)(temp1 & 0xFF);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1);
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temp = (u8)(temp1 >> 8);
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1);
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/* Set TPI input bus and pixel repetition data */
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temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
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TPI_INBUS_RISING_EDGE;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1);
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/* Set TPI AVI Input format data */
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temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
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TPI_INPUT_CLR_RGB;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1);
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/* Set TPI AVI Output format data */
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temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
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TPI_OUTPUT_CLR_HDMI_RGB;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1);
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/* Set TPI audio configuration write data */
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temp = TPI_AUDIO_PASS_BASIC;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1);
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temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
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TPI_AUDIO_TYPE_PCM;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1);
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temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
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i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
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return 0;
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}
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