upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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328 lines
7.8 KiB
328 lines
7.8 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2011 Freescale Semiconductor
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* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* This file provides support for the QIXIS of some Freescale reference boards.
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#include <linux/time.h>
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#include <i2c.h>
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#include "qixis.h"
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#ifndef QIXIS_LBMAP_BRDCFG_REG
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/*
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* For consistency with existing platforms
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*/
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#define QIXIS_LBMAP_BRDCFG_REG 0x00
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#endif
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#ifdef CONFIG_SYS_I2C_FPGA_ADDR
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u8 qixis_read_i2c(unsigned int reg)
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{
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return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
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}
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void qixis_write_i2c(unsigned int reg, u8 value)
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{
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u8 val = value;
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i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
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}
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#endif
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#ifdef QIXIS_BASE
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u8 qixis_read(unsigned int reg)
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{
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void *p = (void *)QIXIS_BASE;
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return in_8(p + reg);
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}
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void qixis_write(unsigned int reg, u8 value)
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{
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void *p = (void *)QIXIS_BASE;
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out_8(p + reg, value);
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}
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#endif
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u16 qixis_read_minor(void)
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{
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u16 minor;
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/* this data is in little endian */
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QIXIS_WRITE(tagdata, 5);
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minor = QIXIS_READ(tagdata);
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QIXIS_WRITE(tagdata, 6);
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minor += QIXIS_READ(tagdata) << 8;
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return minor;
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}
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char *qixis_read_time(char *result)
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{
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time_t time = 0;
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int i;
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/* timestamp is in 32-bit big endian */
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for (i = 8; i <= 11; i++) {
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QIXIS_WRITE(tagdata, i);
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time = (time << 8) + QIXIS_READ(tagdata);
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}
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return ctime_r(&time, result);
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}
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char *qixis_read_tag(char *buf)
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{
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int i;
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char tag, *ptr = buf;
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for (i = 16; i <= 63; i++) {
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QIXIS_WRITE(tagdata, i);
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tag = QIXIS_READ(tagdata);
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*(ptr++) = tag;
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if (!tag)
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break;
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}
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if (i > 63)
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*ptr = '\0';
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return buf;
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}
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/*
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* return the string of binary of u8 in the format of
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* 1010 10_0. The masked bit is filled as underscore.
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*/
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const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
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{
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char *ptr;
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int i;
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ptr = buf;
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for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
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*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
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*(ptr++) = ' ';
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for (i = 0x08; i > 0 ; i >>= 1, ptr++)
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*ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
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*ptr = '\0';
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return buf;
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}
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#ifdef QIXIS_RST_FORCE_MEM
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void board_assert_mem_reset(void)
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{
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u8 rst;
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rst = QIXIS_READ(rst_frc[0]);
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if (!(rst & QIXIS_RST_FORCE_MEM))
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QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM);
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}
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void board_deassert_mem_reset(void)
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{
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u8 rst;
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rst = QIXIS_READ(rst_frc[0]);
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if (rst & QIXIS_RST_FORCE_MEM)
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QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM);
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}
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#endif
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#ifndef CONFIG_SPL_BUILD
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static void qixis_reset(void)
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{
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QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
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}
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static void qixis_bank_reset(void)
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{
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QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
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QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
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}
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static void __maybe_unused set_lbmap(int lbmap)
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{
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u8 reg;
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reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
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reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
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QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
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}
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static void __maybe_unused set_rcw_src(int rcw_src)
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{
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u8 reg;
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reg = QIXIS_READ(dutcfg[1]);
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reg = (reg & ~1) | (rcw_src & 1);
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QIXIS_WRITE(dutcfg[1], reg);
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QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff);
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}
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static void qixis_dump_regs(void)
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{
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int i;
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printf("id = %02x\n", QIXIS_READ(id));
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printf("arch = %02x\n", QIXIS_READ(arch));
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printf("scver = %02x\n", QIXIS_READ(scver));
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printf("model = %02x\n", QIXIS_READ(model));
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printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl));
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printf("aux = %02x\n", QIXIS_READ(aux));
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for (i = 0; i < 16; i++)
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printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i]));
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for (i = 0; i < 16; i++)
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printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i]));
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printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
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QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
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printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]),
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QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2]));
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printf("aux = %02x\n", QIXIS_READ(aux));
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printf("watch = %02x\n", QIXIS_READ(watch));
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printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
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printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
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printf("present = %02x\n", QIXIS_READ(present));
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printf("present2 = %02x\n", QIXIS_READ(present2));
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printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
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printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
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printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
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printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
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}
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void __weak qixis_dump_switch(void)
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{
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puts("Reverse engineering switch is not implemented for this board\n");
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}
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static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int i;
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if (argc <= 1) {
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set_lbmap(QIXIS_LBMAP_DFLTBANK);
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qixis_reset();
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} else if (strcmp(argv[1], "altbank") == 0) {
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set_lbmap(QIXIS_LBMAP_ALTBANK);
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qixis_bank_reset();
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} else if (strcmp(argv[1], "nand") == 0) {
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#ifdef QIXIS_LBMAP_NAND
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QIXIS_WRITE(rst_ctl, 0x30);
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QIXIS_WRITE(rcfg_ctl, 0);
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set_lbmap(QIXIS_LBMAP_NAND);
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set_rcw_src(QIXIS_RCW_SRC_NAND);
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QIXIS_WRITE(rcfg_ctl, 0x20);
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QIXIS_WRITE(rcfg_ctl, 0x21);
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#else
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printf("Not implemented\n");
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#endif
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} else if (strcmp(argv[1], "sd") == 0) {
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#ifdef QIXIS_LBMAP_SD
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QIXIS_WRITE(rst_ctl, 0x30);
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QIXIS_WRITE(rcfg_ctl, 0);
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set_lbmap(QIXIS_LBMAP_SD);
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set_rcw_src(QIXIS_RCW_SRC_SD);
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QIXIS_WRITE(rcfg_ctl, 0x20);
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QIXIS_WRITE(rcfg_ctl, 0x21);
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#else
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printf("Not implemented\n");
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#endif
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} else if (strcmp(argv[1], "ifc") == 0) {
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#ifdef QIXIS_LBMAP_IFC
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QIXIS_WRITE(rst_ctl, 0x30);
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QIXIS_WRITE(rcfg_ctl, 0);
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set_lbmap(QIXIS_LBMAP_IFC);
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set_rcw_src(QIXIS_RCW_SRC_IFC);
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QIXIS_WRITE(rcfg_ctl, 0x20);
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QIXIS_WRITE(rcfg_ctl, 0x21);
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#else
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printf("Not implemented\n");
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#endif
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} else if (strcmp(argv[1], "emmc") == 0) {
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#ifdef QIXIS_LBMAP_EMMC
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QIXIS_WRITE(rst_ctl, 0x30);
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QIXIS_WRITE(rcfg_ctl, 0);
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set_lbmap(QIXIS_LBMAP_EMMC);
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set_rcw_src(QIXIS_RCW_SRC_EMMC);
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QIXIS_WRITE(rcfg_ctl, 0x20);
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QIXIS_WRITE(rcfg_ctl, 0x21);
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#else
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printf("Not implemented\n");
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#endif
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} else if (strcmp(argv[1], "sd_qspi") == 0) {
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#ifdef QIXIS_LBMAP_SD_QSPI
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QIXIS_WRITE(rst_ctl, 0x30);
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QIXIS_WRITE(rcfg_ctl, 0);
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set_lbmap(QIXIS_LBMAP_SD_QSPI);
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set_rcw_src(QIXIS_RCW_SRC_SD);
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qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
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qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
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#else
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printf("Not implemented\n");
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#endif
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} else if (strcmp(argv[1], "qspi") == 0) {
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#ifdef QIXIS_LBMAP_QSPI
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QIXIS_WRITE(rst_ctl, 0x30);
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QIXIS_WRITE(rcfg_ctl, 0);
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set_lbmap(QIXIS_LBMAP_QSPI);
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set_rcw_src(QIXIS_RCW_SRC_QSPI);
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qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20);
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qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21);
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#else
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printf("Not implemented\n");
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#endif
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} else if (strcmp(argv[1], "watchdog") == 0) {
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static char *period[9] = {"2s", "4s", "8s", "16s", "32s",
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"1min", "2min", "4min", "8min"};
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u8 rcfg = QIXIS_READ(rcfg_ctl);
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if (argv[2] == NULL) {
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printf("qixis watchdog <watchdog_period>\n");
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE(period); i++) {
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if (strcmp(argv[2], period[i]) == 0) {
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/* disable watchdog */
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QIXIS_WRITE(rcfg_ctl,
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rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
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QIXIS_WRITE(watch, ((i<<2) - 1));
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QIXIS_WRITE(rcfg_ctl, rcfg);
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return 0;
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}
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}
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} else if (strcmp(argv[1], "dump") == 0) {
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qixis_dump_regs();
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return 0;
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} else if (strcmp(argv[1], "switch") == 0) {
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qixis_dump_switch();
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return 0;
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} else {
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printf("Invalid option: %s\n", argv[1]);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd,
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"Reset the board using the FPGA sequencer",
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"- hard reset to default bank\n"
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"qixis_reset altbank - reset to alternate bank\n"
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"qixis_reset nand - reset to nand\n"
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"qixis_reset sd - reset to sd\n"
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"qixis_reset sd_qspi - reset to sd with qspi support\n"
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"qixis_reset qspi - reset to qspi\n"
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"qixis watchdog <watchdog_period> - set the watchdog period\n"
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" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
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"qixis_reset dump - display the QIXIS registers\n"
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"qixis_reset switch - display switch\n"
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);
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#endif
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