upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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77 lines
1.5 KiB
77 lines
1.5 KiB
/*
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* clocks.c - figure out sclk/cclk/vco and such
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <asm/blackfin.h>
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/* Get the voltage input multiplier */
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static u_long cached_vco_pll_ctl, cached_vco;
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u_long get_vco(void)
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{
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u_long msel;
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u_long pll_ctl = bfin_read_PLL_CTL();
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if (pll_ctl == cached_vco_pll_ctl)
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return cached_vco;
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else
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cached_vco_pll_ctl = pll_ctl;
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msel = (pll_ctl >> 9) & 0x3F;
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if (0 == msel)
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msel = 64;
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cached_vco = CONFIG_CLKIN_HZ;
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cached_vco >>= (1 & pll_ctl); /* DF bit */
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cached_vco *= msel;
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return cached_vco;
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}
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/* Get the Core clock */
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static u_long cached_cclk_pll_div, cached_cclk;
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u_long get_cclk(void)
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{
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u_long csel, ssel;
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if (bfin_read_PLL_STAT() & 0x1)
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return CONFIG_CLKIN_HZ;
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ssel = bfin_read_PLL_DIV();
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if (ssel == cached_cclk_pll_div)
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return cached_cclk;
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else
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cached_cclk_pll_div = ssel;
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csel = ((ssel >> 4) & 0x03);
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ssel &= 0xf;
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if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
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cached_cclk = get_vco() / ssel;
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else
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cached_cclk = get_vco() >> csel;
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return cached_cclk;
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}
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/* Get the System clock */
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static u_long cached_sclk_pll_div, cached_sclk;
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u_long get_sclk(void)
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{
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u_long ssel;
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if (bfin_read_PLL_STAT() & 0x1)
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return CONFIG_CLKIN_HZ;
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ssel = bfin_read_PLL_DIV();
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if (ssel == cached_sclk_pll_div)
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return cached_sclk;
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else
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cached_sclk_pll_div = ssel;
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ssel &= 0xf;
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cached_sclk = get_vco() / ssel;
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return cached_sclk;
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}
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