upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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698 lines
25 KiB
698 lines
25 KiB
/*
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* (C) Copyright 2007-2013
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* lwmon5.h - configuration for lwmon5 board
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Liebherr extra version info
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*/
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#define CONFIG_IDENT_STRING " - v2.0"
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_LWMON5 1 /* Board is lwmon5 */
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_440 1 /* ... PPC440 family */
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#ifdef CONFIG_LCD4_LWMON5
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#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
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#define CONFIG_HOSTNAME lcd4_lwmon5
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#else
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#define CONFIG_SYS_TEXT_BASE 0xFFF80000
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#define CONFIG_HOSTNAME lwmon5
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#endif
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#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
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#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
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#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
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#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
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#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
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#define CONFIG_MISC_INIT_R /* Call misc_init_r */
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#define CONFIG_BOARD_RESET /* Call board_reset */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
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#define CONFIG_SYS_LIME_BASE_0 0xc0000000
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#define CONFIG_SYS_LIME_BASE_1 0xc1000000
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#define CONFIG_SYS_LIME_BASE_2 0xc2000000
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#define CONFIG_SYS_LIME_BASE_3 0xc3000000
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#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
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#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
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#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
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#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
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#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
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#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
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#ifndef CONFIG_LCD4_LWMON5
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#define CONFIG_SYS_USB2D0_BASE 0xe0000100
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#define CONFIG_SYS_USB_DEVICE 0xe0000000
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#define CONFIG_SYS_USB_HOST 0xe0000400
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#endif
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/*
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* Initial RAM & stack pointer
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*
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* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
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* the POST_WORD from OCM to a 440EPx register that preserves it's
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* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
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* for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
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*/
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#ifndef CONFIG_LCD4_LWMON5
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#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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#endif
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/* unused GPT0 COMP reg */
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#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
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#define CONFIG_SYS_OCM_SIZE (16 << 10)
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/* 440EPx errata CHIP 11: don't use last 4kbytes */
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#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
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/* Additional registers for watchdog timer post test */
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#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
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#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
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#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
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#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
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#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
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#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
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#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
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#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
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#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
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#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 2 /* Use UART1 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
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/*
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* FLASH related
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH0 0xFC000000
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#define CONFIG_SYS_FLASH1 0xF8000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
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#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
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#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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/*
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* DDR SDRAM
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*/
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#define CONFIG_SYS_MBYTES_SDRAM 256
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#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#ifndef CONFIG_LCD4_LWMON5
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#define CONFIG_DDR_ECC /* enable ECC */
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#endif
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#ifndef CONFIG_LCD4_LWMON5
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
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CONFIG_SYS_POST_CPU | \
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CONFIG_SYS_POST_ECC | \
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CONFIG_SYS_POST_ETHER | \
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CONFIG_SYS_POST_FPU | \
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CONFIG_SYS_POST_I2C | \
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CONFIG_SYS_POST_MEMORY | \
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CONFIG_SYS_POST_OCM | \
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CONFIG_SYS_POST_RTC | \
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CONFIG_SYS_POST_SPR | \
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CONFIG_SYS_POST_UART | \
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CONFIG_SYS_POST_SYSMON | \
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CONFIG_SYS_POST_WATCHDOG | \
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CONFIG_SYS_POST_DSP | \
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CONFIG_SYS_POST_BSPEC1 | \
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CONFIG_SYS_POST_BSPEC2 | \
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CONFIG_SYS_POST_BSPEC3 | \
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CONFIG_SYS_POST_BSPEC4 | \
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CONFIG_SYS_POST_BSPEC5)
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/* Define here the base-addresses of the UARTs to test in POST */
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#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
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CONFIG_SYS_NS16550_COM2 }
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#define CONFIG_POST_UART { \
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"UART test", \
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"uart", \
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"This test verifies the UART operation.", \
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POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
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&uart_post_test, \
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NULL, \
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NULL, \
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CONFIG_SYS_POST_UART \
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}
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#define CONFIG_POST_WATCHDOG { \
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"Watchdog timer test", \
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"watchdog", \
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"This test checks the watchdog timer.", \
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POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
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&lwmon5_watchdog_post_test, \
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NULL, \
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NULL, \
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CONFIG_SYS_POST_WATCHDOG \
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}
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#define CONFIG_POST_BSPEC1 { \
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"dsPIC init test", \
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"dspic_init", \
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"This test returns result of dsPIC READY test run earlier.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_init_post_test, \
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NULL, \
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NULL, \
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CONFIG_SYS_POST_BSPEC1 \
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}
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#define CONFIG_POST_BSPEC2 { \
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"dsPIC test", \
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"dspic", \
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"This test gets result of dsPIC POST and dsPIC version.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_post_test, \
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NULL, \
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NULL, \
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CONFIG_SYS_POST_BSPEC2 \
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}
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#define CONFIG_POST_BSPEC3 { \
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"FPGA test", \
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"fpga", \
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"This test checks FPGA registers and memory.", \
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POST_RAM | POST_ALWAYS | POST_MANUAL, \
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&fpga_post_test, \
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NULL, \
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NULL, \
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CONFIG_SYS_POST_BSPEC3 \
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}
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#define CONFIG_POST_BSPEC4 { \
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"GDC test", \
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"gdc", \
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"This test checks GDC registers and memory.", \
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POST_RAM | POST_ALWAYS | POST_MANUAL,\
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&gdc_post_test, \
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NULL, \
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NULL, \
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CONFIG_SYS_POST_BSPEC4 \
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}
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#define CONFIG_POST_BSPEC5 { \
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"SYSMON1 test", \
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"sysmon1", \
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"This test checks GPIO_62_EPX pin indicating power failure.", \
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POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
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&sysmon1_post_test, \
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NULL, \
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NULL, \
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CONFIG_SYS_POST_BSPEC5 \
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}
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#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
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#define CONFIG_LOGBUFFER
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/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
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#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
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#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#endif
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_PPC4XX
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#define CONFIG_SYS_I2C_PPC4XX_CH0
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
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#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
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#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
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#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
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#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
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#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
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#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
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#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
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/* 64 byte page write mode using*/
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/* last 6 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
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#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
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#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
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#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
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#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
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CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
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CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
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CONFIG_SYS_I2C_DSPIC_ADDR, \
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CONFIG_SYS_I2C_DSPIC_2_ADDR, \
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CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
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CONFIG_SYS_I2C_DSPIC_IO_ADDR }
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/*
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* Pass open firmware flat tree
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*/
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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/* Update size in "reg" property of NOR FLASH device tree nodes */
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#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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#define CONFIG_FIT /* enable FIT image support */
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#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
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#define CONFIG_PREBOOT "setenv bootdelay 15"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hostname=lwmon5\0" \
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"netdev=eth0\0" \
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"unlock=yes\0" \
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"logversion=2\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
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"addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
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"flash_nfs=run nfsargs addip addtty addmisc;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty addmisc;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};" \
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"run nfsargs addip addtty addmisc;bootm\0" \
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"rootpath=/opt/eldk/ppc_4xxFP\0" \
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"bootfile=/tftpboot/lwmon5/uImage\0" \
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"kernel_addr=FC000000\0" \
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"ramdisk_addr=FC180000\0" \
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"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
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"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
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"cp.b 200000 FFF80000 80000\0" \
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"upd=run load update\0" \
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"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
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"autoscr 200000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_IBM_EMAC4_V4 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_PHY_RESET_DELAY 300
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#define CONFIG_HAS_ETH0
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#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 1
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/* Video console */
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MB862xx
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#define CONFIG_VIDEO_MB862xx_ACCEL
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define VIDEO_FB_16BPP_PIXEL_SWAP
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#define VIDEO_FB_16BPP_WORD_SWAP
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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#ifndef CONFIG_LCD4_LWMON5
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/*
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* USB/EHCI
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*/
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#define CONFIG_USB_EHCI /* Enable EHCI USB support */
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#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
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#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
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#define CONFIG_EHCI_MMIO_BIG_ENDIAN
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#define CONFIG_EHCI_DESC_BIG_ENDIAN
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
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#define CONFIG_USB_STORAGE
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#ifndef CONFIG_LCD4_LWMON5
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#ifdef CONFIG_440EPX
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#define CONFIG_CMD_USB
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#endif
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SUPPORT_VFAT
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
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#ifndef CONFIG_LCD4_LWMON5
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#ifndef DEBUG
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#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
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#endif
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#define CONFIG_WD_PERIOD 40000 /* in usec */
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#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the 40x Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
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/*
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* External Bus Controller (EBC) Setup
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*/
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#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x03000280
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
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/* Memory Bank 1 (Lime) initialization */
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#define CONFIG_SYS_EBC_PB1AP 0x01004380
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#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
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/* Memory Bank 2 (FPGA) initialization */
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#define CONFIG_SYS_EBC_PB2AP 0x01004400
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#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
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/* Memory Bank 3 (FPGA2) initialization */
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#define CONFIG_SYS_EBC_PB3AP 0x01004400
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#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
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#define CONFIG_SYS_EBC_CFG 0xb8400000
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/*
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* Graphics (Fujitsu Lime)
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*/
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/* SDRAM Clock frequency adjustment register */
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#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
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#if 1 /* 133MHz is not tested enough, use 100MHz for now */
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/* Lime Clock frequency is to set 100MHz */
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#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
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#else
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/* Lime Clock frequency for 133MHz */
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#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
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#endif
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/* SDRAM Parameter register */
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#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
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/*
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* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
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* and pixel flare on display when 133MHz was configured. According to
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* SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
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* Grade
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*/
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#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
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#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
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#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
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#else
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#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
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#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
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#endif
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/*
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* GPIO Setup
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*/
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#define CONFIG_SYS_GPIO_PHY1_RST 12
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#define CONFIG_SYS_GPIO_FLASH_WP 14
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#define CONFIG_SYS_GPIO_PHY0_RST 22
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#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
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#define CONFIG_SYS_GPIO_DSPIC_READY 51
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#define CONFIG_SYS_GPIO_CAN_ENABLE 53
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#define CONFIG_SYS_GPIO_LSB_ENABLE 54
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#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
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#define CONFIG_SYS_GPIO_HIGHSIDE 56
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#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
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#define CONFIG_SYS_GPIO_BOARD_RESET 58
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#define CONFIG_SYS_GPIO_LIME_S 59
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#define CONFIG_SYS_GPIO_LIME_RST 60
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#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
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#define CONFIG_SYS_GPIO_WATCHDOG 63
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/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
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#ifdef CONFIG_LCD4_LWMON5
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#define GPIO49_VAL 0
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#else
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#define GPIO49_VAL 1
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#endif
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/*
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* PPC440 GPIO Configuration
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*/
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#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
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}, \
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{ \
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/* GPIO Core 1 */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
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} \
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}
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
|
|
* SPL related defines
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*/
|
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#ifdef CONFIG_LCD4_LWMON5
|
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#define CONFIG_SPL_FRAMEWORK
|
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#define CONFIG_SPL_BOARD_INIT
|
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#define CONFIG_SPL_NOR_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
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#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
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#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
|
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#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
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|
#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
|
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#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
|
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#define CONFIG_SPL_SERIAL_SUPPORT
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|
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/* Place BSS for SPL near end of SDRAM */
|
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#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
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#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
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|
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#define CONFIG_SPL_OS_BOOT
|
|
/* Place patched DT blob (fdt) at this address */
|
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#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
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|
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#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
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|
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/* Settings for real U-Boot to be loaded from NOR flash */
|
|
#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_UBOOT_START 0x01002100
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|
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#define CONFIG_SYS_OS_BASE 0xf8000000
|
|
#define CONFIG_SYS_FDT_BASE 0xf87c0000
|
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#endif
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|
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#endif /* __CONFIG_H */
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