upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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316 lines
8.1 KiB
316 lines
8.1 KiB
/*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004-2008
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* Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <version.h>
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#define CONFIG_MPC5xxx 1
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#define CONFIG_MPC5200 1
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#define CFG_MPC5XXX_CLKIN 33000000
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#define BOOTFLAG_COLD 0x01
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#define BOOTFLAG_WARM 0x02
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#define CONFIG_MISC_INIT_R 1
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#define CFG_CACHELINE_SIZE 32
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#ifdef (CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5
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#endif
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#define CONFIG_PSC_CONSOLE 1
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#define CONFIG_BAUDRATE 115200
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#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#undef CONFIG_PCI_SCAN_SHOW
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CFG_XLB_PIPELINING 1
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#define CONFIG_HIGH_BATS 1
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#define MV_CI mvBlueCOUGAR-P
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#define MV_VCI mvBlueCOUGAR-P
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#define MV_FPGA_DATA 0xff860000
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#define MV_FPGA_SIZE 0x0003c886
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#define MV_KERNEL_ADDR 0xffc00000
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#define MV_INITRD_ADDR 0xff900000
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#define MV_INITRD_LENGTH 0x00300000
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#define MV_SCRATCH_ADDR 0x00000000
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#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
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#define MV_AUTOSCR_ADDR 0xff840000
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#define MV_AUTOSCR_ADDR2 0xff850000
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#define MV_DTB_ADDR 0xfffc0000
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define MV_KERNEL_ADDR_RAM 0x00100000
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#define MV_DTB_ADDR_RAM 0x00600000
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#define MV_INITRD_ADDR_RAM 0x01000000
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_CPU "PowerPC,5200@0"
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#define OF_SOC "soc5200@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define MV_DTB_NAME mvbc-p.dtb
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/*
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* Supported commands
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_FPGA
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#undef CONFIG_WATCHDOG
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#define CONFIG_BOOTP_VENDOREX
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_NTPSERVER
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#define CONFIG_BOOTP_RANDOM_DELAY
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/*
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* Autoboot
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*/
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_STOP_STR "s"
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_RESET_TO_RETRY 1000
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#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \
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then autoscr ${autoscr_addr}; \
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else autoscr ${autoscr_addr2}; \
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fi;"
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#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
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#define CONFIG_ENV_OVERWRITE
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#define XMK_STR(x) #x
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#define MK_STR(x) XMK_STR(x)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console_nr=0\0" \
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"console=yes\0" \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0" \
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"fpga=0\0" \
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"fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
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"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
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"autoscr_addr=" MK_STR(MV_AUTOSCR_ADDR) "\0" \
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"autoscr_addr2=" MK_STR(MV_AUTOSCR_ADDR2) "\0" \
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"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
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"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
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"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
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"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
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"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
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"mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
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"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
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"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
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"mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
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"mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
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"mv_version=" U_BOOT_VERSION "\0" \
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"dhcp_client_id=" MK_STR(MV_CI) "\0" \
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"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
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"netretry=no\0" \
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"use_static_ipaddr=no\0" \
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"static_ipaddr=192.168.90.10\0" \
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"static_netmask=255.255.255.0\0" \
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"static_gateway=0.0.0.0\0" \
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"initrd_name=uInitrd.mvbc-p-rfs\0" \
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"zcip=no\0" \
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"netboot=yes\0" \
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"mvtest=Ff\0" \
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"tried_bootfromflash=no\0" \
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"tried_bootfromnet=no\0" \
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"use_dhcp=yes\0" \
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"gev_start=yes\0" \
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"mvbcdma_debug=0\0" \
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"mvbcia_debug=0\0" \
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"propdev_debug=0\0" \
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"gevss_debug=0\0" \
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"watchdog=1\0" \
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""
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#undef XMK_STR
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#undef MK_STR
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/*
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* IPB Bus clocking configuration.
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*/
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#define CFG_IPBCLK_EQUALS_XLBCLK
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#define CFG_PCICLK_EQUALS_IPBCLK_DIV2
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/*
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* Flash configuration
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*/
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#undef CONFIG_FLASH_16BIT
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI_AMD_RESET 1
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_FLASH_ERASE_TOUT 50000
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#define CFG_FLASH_WRITE_TOUT 1000
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 256
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#define CFG_LOWBOOT
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#define CFG_FLASH_BASE TEXT_BASE
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#define CFG_FLASH_SIZE 0x00800000
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/*
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* Environment settings
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*/
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#define CFG_ENV_IS_IN_FLASH
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#undef CFG_FLASH_PROTECTION
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#define CFG_ENV_ADDR 0xFFFE0000
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#define CFG_ENV_SIZE 0x10000
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#define CFG_ENV_SECT_SIZE 0x10000
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
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/*
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* Memory map
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*/
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#define CFG_MBAR 0xF0000000
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_DEFAULT_MBAR 0x80000000
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#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
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#define CFG_GBL_DATA_SIZE 128
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_BASE TEXT_BASE
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT 1
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#endif
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/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
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#define CFG_MONITOR_LEN (512 << 10)
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#define CFG_MALLOC_LEN (512 << 10)
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#define CFG_BOOTMAPSZ (8 << 20)
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/*
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* Ethernet configuration
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_NET_RETRY_COUNT 5
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#define CONFIG_E1000
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#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
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#undef CONFIG_MPC5xxx_FEC
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#undef CONFIG_PHY_ADDR
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#define CONFIG_NETDEV eth0
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_HUSH_PARSER
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#define CONFIG_CMDLINE_EDITING
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#define CFG_PROMPT_HUSH_PS2 "> "
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#undef CFG_LONGHELP
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#define CFG_PROMPT "=> "
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#ifdef (CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024
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#else
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#define CFG_CBSIZE 256
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 16
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#define CFG_BARGSIZE CFG_CBSIZE
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#define CFG_MEMTEST_START 0x00800000
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#define CFG_MEMTEST_END 0x02f00000
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#define CFG_HZ 1000
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/* default load address */
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#define CFG_LOAD_ADDR 0x02000000
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 0x00200000
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/*
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* Various low-level settings
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*/
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#define CFG_GPS_PORT_CONFIG 0x20000004
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#define CFG_HID0_INIT (HID0_ICE | HID0_ICFI)
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#define CFG_HID0_FINAL HID0_ICE
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#define CFG_BOOTCS_START CFG_FLASH_BASE
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#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
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#define CFG_BOOTCS_CFG 0x00047800
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#define CFG_CS0_START CFG_FLASH_BASE
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#define CFG_CS0_SIZE CFG_FLASH_SIZE
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#define CFG_CS_BURST 0x000000f0
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#define CFG_CS_DEADCYCLE 0x33333303
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#define CFG_RESET_ADDRESS 0x00000100
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#undef FPGA_DEBUG
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#undef CFG_FPGA_PROG_FEEDBACK
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#define CONFIG_FPGA CFG_ALTERA_CYCLON2
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#define CONFIG_FPGA_ALTERA 1
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#define CONFIG_FPGA_CYCLON2 1
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#define CONFIG_FPGA_COUNT 1
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#endif
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