upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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461 lines
13 KiB
461 lines
13 KiB
/*
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* MPC8560 FCC Fast Ethernet
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* Copyright (c) 2003 Motorola,Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
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*
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* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* MPC8560 FCC Fast Ethernet
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* Basic ET HW initialization and packet RX/TX routines
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*
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* This code will not perform the IO port configuration. This should be
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* done in the iop_conf_t structure specific for the board.
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*
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* TODO:
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* add a PHY driver to do the negotiation
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* reflect negotiation results in FPSMR
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* look for ways to configure the board specific stuff elsewhere, eg.
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* config_xxx.h or the board directory
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/cpm_85xx.h>
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#include <command.h>
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#include <config.h>
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#include <net.h>
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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#include <miiphy.h>
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#endif
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#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET)
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static struct ether_fcc_info_s
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{
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int ether_index;
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int proff_enet;
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ulong cpm_cr_enet_sblock;
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ulong cpm_cr_enet_page;
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ulong cmxfcr_mask;
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ulong cmxfcr_value;
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}
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ether_fcc_info[] =
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{
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#ifdef CONFIG_ETHER_ON_FCC1
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{
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0,
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PROFF_FCC1,
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CPM_CR_FCC1_SBLOCK,
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CPM_CR_FCC1_PAGE,
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CONFIG_SYS_CMXFCR_MASK1,
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CONFIG_SYS_CMXFCR_VALUE1
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},
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#endif
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#ifdef CONFIG_ETHER_ON_FCC2
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{
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1,
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PROFF_FCC2,
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CPM_CR_FCC2_SBLOCK,
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CPM_CR_FCC2_PAGE,
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CONFIG_SYS_CMXFCR_MASK2,
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CONFIG_SYS_CMXFCR_VALUE2
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},
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#endif
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#ifdef CONFIG_ETHER_ON_FCC3
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{
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2,
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PROFF_FCC3,
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CPM_CR_FCC3_SBLOCK,
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CPM_CR_FCC3_PAGE,
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CONFIG_SYS_CMXFCR_MASK3,
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CONFIG_SYS_CMXFCR_VALUE3
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},
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#endif
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};
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/*---------------------------------------------------------------------*/
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/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
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#define PKT_MAXDMA_SIZE 1520
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/* The FCC stores dest/src/type, data, and checksum for receive packets. */
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MINBUF_SIZE 64
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/* Maximum input buffer size. Must be a multiple of 32. */
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#define PKT_MAXBLR_SIZE 1536
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#define TOUT_LOOP 1000000
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#define TX_BUF_CNT 2
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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/*
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* FCC Ethernet Tx and Rx buffer descriptors.
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* Provide for Double Buffering
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* Note: PKTBUFSRX is defined in net.h
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*/
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typedef volatile struct rtxbd {
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cbd_t rxbd[PKTBUFSRX];
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cbd_t txbd[TX_BUF_CNT];
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} RTXBD;
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/* Good news: the FCC supports external BDs! */
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#ifdef __GNUC__
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static RTXBD rtx __attribute__ ((aligned(8)));
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#else
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#error "rtx must be 64-bit aligned"
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#endif
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#undef ET_DEBUG
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static int fec_send(struct eth_device *dev, void *packet, int length)
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{
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int i = 0;
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int result = 0;
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if (length <= 0) {
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printf("fec: bad packet size: %d\n", length);
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goto out;
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}
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for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
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if (i >= TOUT_LOOP) {
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printf("fec: tx buffer not ready\n");
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goto out;
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}
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}
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rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
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rtx.txbd[txIdx].cbd_datlen = length;
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rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
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BD_ENET_TX_TC | BD_ENET_TX_PAD);
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for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
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if (i >= TOUT_LOOP) {
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printf("fec: tx error\n");
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goto out;
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}
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}
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#ifdef ET_DEBUG
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printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
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printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
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for(i=0;i<(length/16 + 1);i++) {
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printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
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*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
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*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
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}
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#endif
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/* return only status bits */
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result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
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txIdx = (txIdx + 1) % TX_BUF_CNT;
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out:
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return result;
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}
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static int fec_recv(struct eth_device* dev)
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{
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int length;
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for (;;)
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{
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if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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length = -1;
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break; /* nothing received - leave for() loop */
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}
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length = rtx.rxbd[rxIdx].cbd_datlen;
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if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
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printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
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}
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else {
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/* Pass the packet up to the protocol layers. */
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net_process_received_packet(net_rx_packets[rxIdx], length - 4);
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}
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/* Give the buffer back to the FCC. */
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rtx.rxbd[rxIdx].cbd_datlen = 0;
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/* wrap around buffer index when necessary */
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if ((rxIdx + 1) >= PKTBUFSRX) {
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rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
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rxIdx = 0;
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}
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else {
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rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
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rxIdx++;
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}
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}
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return length;
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}
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static int fec_init(struct eth_device* dev, bd_t *bis)
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{
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struct ether_fcc_info_s * info = dev->priv;
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int i;
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp);
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fcc_enet_t *pram_ptr;
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unsigned long mem_addr;
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#if 0
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mii_discover_phy();
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#endif
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/* 28.9 - (1-2): ioports have been set up already */
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/* 28.9 - (3): connect FCC's tx and rx clocks */
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cpm->im_cpm_mux.cmxuar = 0; /* ATM */
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cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
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info->cmxfcr_value;
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/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
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if(info->ether_index == 0) {
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cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
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} else if (info->ether_index == 1) {
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cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
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} else if (info->ether_index == 2) {
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cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
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}
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/* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
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if(info->ether_index == 0) {
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cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
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} else if (info->ether_index == 1){
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cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
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} else if (info->ether_index == 2){
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cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC;
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}
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/* 28.9 - (6): FDSR: Ethernet Syn */
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if(info->ether_index == 0) {
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cpm->im_cpm_fcc1.fdsr = 0xD555;
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} else if (info->ether_index == 1) {
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cpm->im_cpm_fcc2.fdsr = 0xD555;
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} else if (info->ether_index == 2) {
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cpm->im_cpm_fcc3.fdsr = 0xD555;
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}
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/* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
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rxIdx = 0;
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txIdx = 0;
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/* Setup Receiver Buffer Descriptors */
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for (i = 0; i < PKTBUFSRX; i++)
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{
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rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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rtx.rxbd[i].cbd_datlen = 0;
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rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
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}
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rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/* Setup Ethernet Transmitter Buffer Descriptors */
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for (i = 0; i < TX_BUF_CNT; i++)
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{
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rtx.txbd[i].cbd_sc = 0;
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rtx.txbd[i].cbd_datlen = 0;
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rtx.txbd[i].cbd_bufaddr = 0;
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}
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rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/* 28.9 - (7): initialize parameter ram */
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pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]);
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/* clear whole structure to make sure all reserved fields are zero */
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memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
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/*
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* common Parameter RAM area
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*
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* Allocate space in the reserved FCC area of DPRAM for the
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* internal buffers. No one uses this space (yet), so we
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* can do this. Later, we will add resource management for
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* this area.
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* CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560
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* 0x9000 for MPC8541, MPC8555
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*/
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mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
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pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
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pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
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/*
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* Set maximum bytes per receive buffer.
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* It must be a multiple of 32.
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*/
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pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
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/* localbus SDRAM should be preferred */
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pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
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CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
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pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
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pram_ptr->fen_genfcc.fcc_rbdstat = 0;
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pram_ptr->fen_genfcc.fcc_rbdlen = 0;
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pram_ptr->fen_genfcc.fcc_rdptr = 0;
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/* localbus SDRAM should be preferred */
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pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
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CONFIG_SYS_CPMFCR_RAMTYPE) << 24;
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pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
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pram_ptr->fen_genfcc.fcc_tbdstat = 0;
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pram_ptr->fen_genfcc.fcc_tbdlen = 0;
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pram_ptr->fen_genfcc.fcc_tdptr = 0;
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/* protocol-specific area */
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pram_ptr->fen_statbuf = 0x0;
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pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
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pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
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pram_ptr->fen_crcec = 0;
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pram_ptr->fen_alec = 0;
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pram_ptr->fen_disfc = 0;
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pram_ptr->fen_retlim = 15; /* Retry limit threshold */
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pram_ptr->fen_retcnt = 0;
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pram_ptr->fen_pper = 0;
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pram_ptr->fen_boffcnt = 0;
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pram_ptr->fen_gaddrh = 0;
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pram_ptr->fen_gaddrl = 0;
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pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
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/*
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* Set Ethernet station address.
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*
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* This is supplied in the board information structure, so we
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* copy that into the controller.
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* So far we have only been given one Ethernet address. We make
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* it unique by setting a few bits in the upper byte of the
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* non-static part of the address.
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*/
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#define ea eth_get_ethaddr()
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pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
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pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
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pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
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#undef ea
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pram_ptr->fen_ibdcount = 0;
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pram_ptr->fen_ibdstart = 0;
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pram_ptr->fen_ibdend = 0;
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pram_ptr->fen_txlen = 0;
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pram_ptr->fen_iaddrh = 0; /* disable hash */
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pram_ptr->fen_iaddrl = 0;
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pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
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/* pad pointer. use tiptr since we don't need a specific padding char */
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pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
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pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
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pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
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#if defined(ET_DEBUG)
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printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
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printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
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pram_ptr->fen_genfcc.fcc_rbase);
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printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
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pram_ptr->fen_genfcc.fcc_tbase);
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#endif
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/* 28.9 - (8)(9): clear out events in FCCE */
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/* 28.9 - (9): FCCM: mask all events */
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if(info->ether_index == 0) {
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cpm->im_cpm_fcc1.fcce = ~0x0;
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cpm->im_cpm_fcc1.fccm = 0;
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} else if (info->ether_index == 1) {
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cpm->im_cpm_fcc2.fcce = ~0x0;
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cpm->im_cpm_fcc2.fccm = 0;
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} else if (info->ether_index == 2) {
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cpm->im_cpm_fcc3.fcce = ~0x0;
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cpm->im_cpm_fcc3.fccm = 0;
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}
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/* 28.9 - (10-12): we don't use ethernet interrupts */
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/* 28.9 - (13)
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*
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* Let's re-initialize the channel now. We have to do it later
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* than the manual describes because we have just now finished
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* the BD initialization.
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*/
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cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
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info->cpm_cr_enet_sblock,
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0x0c,
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CPM_CR_INIT_TRX) | CPM_CR_FLG;
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do {
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__asm__ __volatile__ ("eieio");
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} while (cp->cpcr & CPM_CR_FLG);
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/* 28.9 - (14): enable tx/rx in gfmr */
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if(info->ether_index == 0) {
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cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
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} else if (info->ether_index == 1) {
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cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
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} else if (info->ether_index == 2) {
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cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
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}
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return 1;
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}
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static void fec_halt(struct eth_device* dev)
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{
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struct ether_fcc_info_s * info = dev->priv;
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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/* write GFMR: disable tx/rx */
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if(info->ether_index == 0) {
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cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
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} else if(info->ether_index == 1) {
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cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
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} else if(info->ether_index == 2) {
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cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
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}
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}
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int fec_initialize(bd_t *bis)
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{
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struct eth_device* dev;
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int i;
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for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
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{
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dev = (struct eth_device*) malloc(sizeof *dev);
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memset(dev, 0, sizeof *dev);
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sprintf(dev->name, "FCC%d",
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ether_fcc_info[i].ether_index + 1);
|
|
dev->priv = ðer_fcc_info[i];
|
|
dev->init = fec_init;
|
|
dev->halt = fec_halt;
|
|
dev->send = fec_send;
|
|
dev->recv = fec_recv;
|
|
|
|
eth_register(dev);
|
|
|
|
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
|
|
&& defined(CONFIG_BITBANGMII)
|
|
int retval;
|
|
struct mii_dev *mdiodev = mdio_alloc();
|
|
if (!mdiodev)
|
|
return -ENOMEM;
|
|
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
|
|
mdiodev->read = bb_miiphy_read;
|
|
mdiodev->write = bb_miiphy_write;
|
|
|
|
retval = mdio_register(mdiodev);
|
|
if (retval < 0)
|
|
return retval;
|
|
#endif
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
#endif
|
|
|