upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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116 lines
3.1 KiB
116 lines
3.1 KiB
/*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx35_pins.h>
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#include <asm/arch/iomux.h>
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/*
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* IOMUX register (base) addresses
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*/
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enum iomux_reg_addr {
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IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */
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IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */
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IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */
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IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */
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IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */
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IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */
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IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */
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};
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#define MUX_PIN_NUM_MAX \
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(((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
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#define MUX_INPUT_NUM_MUX \
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(((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
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#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2)
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/*
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* Request ownership for an IO pin. This function has to be the first one
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* being called before that pin is used.
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*/
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void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
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{
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u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
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if (mux_reg != NON_MUX_I) {
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mux_reg += IOMUXGPR;
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writel(cfg, mux_reg);
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}
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}
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/*
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* Release ownership for an IO pin
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*/
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void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
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{
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}
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/*
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* This function configures the pad value for a IOMUX pin.
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*
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* @param pin a pin number as defined in iomux_pin_name_t
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* @param config the ORed value of elements defined in iomux_pad_config_t
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*/
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void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
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{
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u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
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writel(config, pad_reg);
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}
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/*
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* This function enables/disables the general purpose function for a particular
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* signal.
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*
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* @param gp one signal as defined in iomux_gp_func_t
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* @param en enable/disable
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*/
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void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
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{
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u32 l;
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l = readl(IOMUXGPR);
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if (en)
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l |= gp;
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else
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l &= ~gp;
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writel(l, IOMUXGPR);
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}
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/*
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* This function configures input path.
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*
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* @param input index of input select register as defined in
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* iomux_input_select_t
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* @param config the binary value of elements defined in
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* iomux_input_config_t
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*/
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void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
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{
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u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
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writel(config, reg);
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}
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